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On the other hand, large arrays of FPGA-based accelerators are too inefficient to cover the needs of cost sensitive professional markets. We present a new architecture composed of a network of configurable flexible weakly programmable processing elements, Flexible Weakly programmable Advanced Film Engine (FlexWAFE). This architecture delivers both programmability and high efficiency when implemented on an FPGA basis. We demonstrate these claims using a professional next-generation noise reducer with more than 170G image operations\/s at 80% FPGA area utilization on four Virtex II-Pro FPGAs. This article will focus on the FlexWAFE architecture principle and implementation on a PCI-Express board.<\/jats:p>","DOI":"10.1145\/1596532.1596536","type":"journal-article","created":{"date-parts":[[2009,10,27]],"date-time":"2009-10-27T13:28:14Z","timestamp":1256650094000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Application development with the FlexWAFE real-time stream processing architecture for FPGAs"],"prefix":"10.1145","volume":"9","author":[{"given":"Amilcar Do Carmo","family":"Lucas","sequence":"first","affiliation":[{"name":"Technical University of Braunschweig, Germany"}]},{"given":"Henning","family":"Sahlbach","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig, Germany"}]},{"given":"Sean","family":"Whitty","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig, Germany"}]},{"given":"Sven","family":"Heithecker","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig, Germany"}]},{"given":"Rolf","family":"Ernst","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig, Germany"}]}],"member":"320","published-online":{"date-parts":[[2009,10,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1028176.1006734"},{"key":"e_1_2_1_2_1","unstructured":"Aspex Ltd. 2008. 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