{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:52:29Z","timestamp":1750308749235,"version":"3.41.0"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2009,11,1]],"date-time":"2009-11-01T00:00:00Z","timestamp":1257033600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS-0719936"],"award-info":[{"award-number":["CNS-0719936"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2009,11]]},"abstract":"<jats:p>Rapid progress on nanodevices points to a promising direction for future circuit design. However, since nanofabrication techniques are not yet mature, implementation of nanocircuits, at least on a large scale, in the near future is infeasible. To ease fabrication and overcome the problem of high defect levels in nanotechnology, hybrid nano\/CMOS reconfigurable architectures are attractive choices. Moreover, if the current photolithography fabrication process can be used to manufacture the hybrid chips, the benefits of nanotechnologies can be realized today.<\/jats:p>\n          <jats:p>Traditional reconfigurable architectures can only support partial or coarse-grain runtime reconfiguration due to their limited on-chip storage and long off-chip reconfiguration latency. Recent progress on nano Random Access Memories (RAMs), such as carbon nanotube-based RAM (NRAM), Phase-Change Memory (PCM), magnetoresistive RAM (MRAM), etc., provides us with a chance to realize on-chip fine-grain runtime reconfiguration. These nano RAMs have good compatibility with the current fabrication process. By utilizing them in the hybrid design, we can take advantage of both CMOS and nanotechnology, and greatly improve the logic density, resource utilization, and performance of our design.<\/jats:p>\n          <jats:p>In this article, we propose a high-performance reconfigurable architecture, called NATURE, that utilizes CMOS logic and nano RAMs. An automatic design flow for NATURE is presented in Part II of the article. In NATURE, the highly dense nonvolatile nano RAMs are distributed throughout the chip to allow large embedded on-chip configuration storage, which enables fast reading and hence supports fine-grain runtime reconfiguration and temporal logic folding of a circuit before being mapped to the architecture. Temporal logic folding can significantly increase the logic density of NATURE (by over an order of magnitude for large circuits) while remaining competitive in performance and power consumption. For ease of exposition, we use NRAMs to illustrate various concepts in this article due to the excellent properties of NRAMs. However, other nano RAMs can also be used instead. Experimental results based on NRAMs establish the efficacy of NATURE.<\/jats:p>","DOI":"10.1145\/1629091.1629092","type":"journal-article","created":{"date-parts":[[2009,11,30]],"date-time":"2009-11-30T14:56:36Z","timestamp":1259592996000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["A hybrid nano\/CMOS dynamically reconfigurable system\u2014Part I"],"prefix":"10.1145","volume":"5","author":[{"given":"Wei","family":"Zhang","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Li","family":"Shang","sequence":"additional","affiliation":[{"name":"University of Colorado, Boulder, Boulder, CO"}]}],"member":"320","published-online":{"date-parts":[[2009,11,30]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1109\/54.655177"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1145\/296399.296428"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1142\/S0218126604001222"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1109\/TNANO.2003.808503"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1145\/774572.774636"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1063\/1.336109"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1109\/92.766746"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1021\/nl025875l"},{"volume-title":"Proceedings of the 4th Canadian Workshop of Field-Programmable Devices. 47--54","year":"1996","author":"DeHon A.","key":"e_1_2_1_9_1"},{"volume-title":"Proceedings of the International Conference on Nano-Networks. 1--5.","year":"2006","author":"DeHon A.","key":"e_1_2_1_10_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1109\/TVLSI.2004.827562"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1145\/968280.968299"},{"key":"e_1_2_1_13_1","first-page":"40","article-title":"Toggle magnetic random access memory cells scalable to a capacity of over 100 megabits","volume":"103","author":"Fukumoto Y.","year":"2008","journal-title":"Amer. Instit. Phys."},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1145\/379240.379262"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/2.839324"},{"volume-title":"Proceedings of the Conference on VLSI Technology, System and Applications. 1--4.","author":"Ha D.","key":"e_1_2_1_16_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1109\/TVLSI.2003.821545"},{"unstructured":"ITRS. 2007. International Technology Roadmap for Semiconductors. http:\/\/public.itrs.net.  ITRS. 2007. International Technology Roadmap for Semiconductors. http:\/\/public.itrs.net.","key":"e_1_2_1_18_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1021\/nl035185x"},{"doi-asserted-by":"publisher","key":"e_1_2_1_20_1","DOI":"10.1145\/774572.774593"},{"key":"e_1_2_1_21_1","first-page":"896","article-title":"Macro model and sense amplifier for a MRAM","volume":"41","author":"Kim J.-H.","year":"2002","journal-title":"J. Korean Phys. Soc."},{"doi-asserted-by":"publisher","key":"e_1_2_1_22_1","DOI":"10.1109\/IEDM.2003.1269271"},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 472--473","author":"Lee K.-J.","key":"e_1_2_1_23_1"},{"volume-title":"Logic synthesis and optimization benchmarks. Tech. rep","author":"Lisanke R.","key":"e_1_2_1_24_1"},{"volume-title":"Proceedings of the International Conference on Field-Programmable Logic and Applications. 61--70","author":"Mei B.","key":"e_1_2_1_25_1"},{"unstructured":"Nantero. 2008. Nantero. http:\/\/www.nantero.com.  Nantero. 2008. Nantero. http:\/\/www.nantero.com.","key":"e_1_2_1_26_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_27_1","DOI":"10.1109\/5.231340"},{"doi-asserted-by":"publisher","key":"e_1_2_1_28_1","DOI":"10.1126\/science.289.5476.94"},{"volume-title":"Proceedings of the International Workshop on Memory Technology, Design and Testing. 86--91","author":"Salamon D.","key":"e_1_2_1_29_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_30_1","DOI":"10.1063\/1.2821845"},{"doi-asserted-by":"publisher","key":"e_1_2_1_31_1","DOI":"10.1145\/503048.503072"},{"volume-title":"Proceedings of the Aerospace Conference 1--5.","author":"Smith R. F.","key":"e_1_2_1_32_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_33_1","DOI":"10.1088\/0957-4484\/15\/8\/003"},{"doi-asserted-by":"crossref","unstructured":"Snider G. S. and Williams R. S. 2007. Nano\/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnol. 18 art.035204.  Snider G. S. and Williams R. S. 2007. Nano\/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnol. 18 art.035204.","key":"e_1_2_1_34_1","DOI":"10.1088\/0957-4484\/18\/3\/035204"},{"doi-asserted-by":"crossref","unstructured":"Stix G. 2005. Nanotubes in the clean room. Sci. Amer. 82--85.  Stix G. 2005. Nanotubes in the clean room. Sci. Amer. 82--85.","key":"e_1_2_1_35_1","DOI":"10.1038\/scientificamerican0205-82"},{"doi-asserted-by":"publisher","key":"e_1_2_1_36_1","DOI":"10.1088\/0957-4484\/16\/6\/045"},{"doi-asserted-by":"publisher","key":"e_1_2_1_37_1","DOI":"10.1093\/ietele\/e90-c.10.1936"},{"unstructured":"Synopsys. 2009. Synopsys. http:\/\/www.synopsys.com.  Synopsys. 2009. Synopsys. http:\/\/www.synopsys.com.","key":"e_1_2_1_38_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_39_1","DOI":"10.1109\/JPROC.2003.811804"},{"volume-title":"Proceedings of the 10th International Workshop on Field Programmable Logic and Applications. 535--544","author":"Tessier R.","key":"e_1_2_1_40_1"},{"volume-title":"Proceedings of the Symposium on FPGAs for Custom Computing Machines. 22--28","author":"Trimberger S.","key":"e_1_2_1_41_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_42_1","DOI":"10.1049\/mnl:20070034"},{"doi-asserted-by":"publisher","key":"e_1_2_1_43_1","DOI":"10.1140\/epjb\/e2007-00154-y"},{"doi-asserted-by":"publisher","key":"e_1_2_1_44_1","DOI":"10.1109\/ICCD.2005.21"},{"doi-asserted-by":"publisher","key":"e_1_2_1_45_1","DOI":"10.1145\/1146909.1147091"},{"doi-asserted-by":"publisher","key":"e_1_2_1_46_1","DOI":"10.1145\/1278480.1278558"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629091.1629092","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629091.1629092","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:19Z","timestamp":1750278139000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629091.1629092"}},"subtitle":["Architecture"],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":46,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2009,11]]}},"alternative-id":["10.1145\/1629091.1629092"],"URL":"https:\/\/doi.org\/10.1145\/1629091.1629092","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2009,11]]},"assertion":[{"value":"2008-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-11-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}