{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,4]],"date-time":"2026-10-04T20:35:21Z","timestamp":1791146121405,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,10,11]],"date-time":"2009-10-11T00:00:00Z","timestamp":1255219200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,10,11]]},"DOI":"10.1145\/1629435.1629480","type":"proceedings-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T15:11:11Z","timestamp":1255446671000},"page":"325-334","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems"],"prefix":"10.1145","author":[{"given":"Vincenzo","family":"Rana","sequence":"first","affiliation":[{"name":"Politecnico di Milano, Milano, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Srinivasan","family":"Murali","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marco Domenico","family":"Santambrogio","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"Universit\u00e0 di Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donatella","family":"Sciuto","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milano, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2009,10,11]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"2009","volume-title":"Automation and Test in Europe Conference and Exhibition","author":"Flamand E.","year":"2009","unstructured":"Flamand , E. : Strategic directions towards multicore application specific computing. Design , Automation and Test in Europe Conference and Exhibition , 2009 ( 2009 ) Flamand, E.: Strategic directions towards multicore application specific computing. Design, Automation and Test in Europe Conference and Exhibition, 2009 (2009)"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883909"},{"key":"e_1_3_2_1_3_1","volume-title":"Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (April 2008)","author":"Hubner M.","unstructured":"Hubner , M. , Braun , L. , Gohringer , D. , Becker , J. : Run-time reconfigurable adaptive multilayer network-on-chip for fpga-based systems . Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (April 2008) 1--6 Hubner, M., Braun, L., Gohringer, D., Becker, J.: Run-time reconfigurable adaptive multilayer network-on-chip for fpga-based systems. Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (April 2008) 1--6"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICESS.2008.20"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.888404"},{"key":"e_1_3_2_1_6_1","volume-title":"Field Programmable Logic and Applications, 2006. FPL '06. International Conference on (Aug. 2006)","author":"Singhal L.","unstructured":"Singhal , L. , Bozorgzadeh , E. : Multi-layer floorplanning on a sequence of reconfigurable designs . Field Programmable Logic and Applications, 2006. FPL '06. International Conference on (Aug. 2006) 1--8 Singhal, L., Bozorgzadeh, E.: Multi-layer floorplanning on a sequence of reconfigurable designs. Field Programmable Logic and Applications, 2006. FPL '06. International Conference on (Aug. 2006) 1--8"},{"key":"e_1_3_2_1_7_1","volume-title":"Automation and Test in Europe Conference and Exhibition, 2004. Proceedings 2 (Feb. 2004)","volume":"2","author":"Murali S.","unstructured":"Murali , S. , De Micheli , G. : Bandwidth-constrained mapping of cores onto noc architectures. Design , Automation and Test in Europe Conference and Exhibition, 2004. Proceedings 2 (Feb. 2004) 896--901 Vol. 2 Murali, S., De Micheli, G.: Bandwidth-constrained mapping of cores onto noc architectures. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings 2 (Feb. 2004) 896--901 Vol.2"},{"key":"e_1_3_2_1_8_1","volume-title":"Automation and Test in Europe, 2006. DATE '06. Proceedings 1 (March 2006)","author":"Murali S.","unstructured":"Murali , S. , Coenen , M. , Radulescu , A. , Goossens , K. , De Micheli , G. : A methodology for mapping multiple use-cases onto networks on chips. Design , Automation and Test in Europe, 2006. DATE '06. Proceedings 1 (March 2006) 1--6 Murali, S., Coenen, M., Radulescu, A., Goossens, K., De Micheli, G.: A methodology for mapping multiple use-cases onto networks on chips. Design, Automation and Test in Europe, 2006. DATE '06. Proceedings 1 (March 2006) 1--6"},{"key":"e_1_3_2_1_9_1","volume-title":": Design and implementation of an fpga-based partially reconfigurable network controller. Master's thesis","author":"Chaubal A.P.","year":"2004","unstructured":"Chaubal , A.P. : Design and implementation of an fpga-based partially reconfigurable network controller. Master's thesis , Virginia Polytechnic Institute and State University ( 2004 ) Chaubal, A.P.: Design and implementation of an fpga-based partially reconfigurable network controller. Master's thesis, Virginia Polytechnic Institute and State University (2004)"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2005.7"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382679"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993398"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450108"},{"key":"e_1_3_2_1_15_1","volume-title":"Approximation algorithms","author":"Vazirani V.","year":"2001","unstructured":"Vazirani , V. : Approximation algorithms . Springer-Verlag ( 2001 ) Vazirani, V.: Approximation algorithms. Springer-Verlag (2001)"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000677"},{"key":"e_1_3_2_1_17_1","volume-title":"Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (April 2008)","author":"Lu Y.","unstructured":"Lu , Y. , Marconi , T. , Gaydadjiev , G. , Bertels , K. , Meeuws , R. : A self-adaptive on-line task placement algorithm for partially reconfigurable systems . Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (April 2008) 1--8 Lu, Y., Marconi, T., Gaydadjiev, G., Bertels, K., Meeuws, R.: A self-adaptive on-line task placement algorithm for partially reconfigurable systems. Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (April 2008) 1--8"},{"key":"e_1_3_2_1_18_1","series-title":"September 2004","volume-title":"Xapp290 -- two flows for partial reconfiguration: Module based or difference based","author":"Xilinx","unstructured":"Xilinx : Xapp290 -- two flows for partial reconfiguration: Module based or difference based ( September 2004 ) Xilinx: Xapp290 -- two flows for partial reconfiguration: Module based or difference based (September 2004)"},{"key":"e_1_3_2_1_19_1","series-title":"March 2006","volume-title":"Early access partial reconfiguration user guide.","author":"Xilinx","unstructured":"Xilinx : Early access partial reconfiguration user guide. ( March 2006 ) Xilinx: Early access partial reconfiguration user guide. (March 2006)"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/224170.224228"},{"key":"e_1_3_2_1_21_1","volume-title":"Computer Design, 2003. Proceedings. 21st International Conference on (Oct. 2003)","author":"Dall'Osso M.","unstructured":"Dall'Osso , M. , Biccari , G. , Giovannini , L. , Bertozzi , D. , Benini , L. : Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor socs . Computer Design, 2003. Proceedings. 21st International Conference on (Oct. 2003) 536--539 Dall'Osso, M., Biccari, G., Giovannini, L., Bertozzi, D., Benini, L.: Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor socs. Computer Design, 2003. Proceedings. 21st International Conference on (Oct. 2003) 536--539"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2004.1330747"}],"event":{"name":"ESWeek '09: Fifth Embedded Systems Week","location":"Grenoble France","acronym":"ESWeek '09","sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 7th IEEE\/ACM international conference on Hardware\/software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629435.1629480","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629435.1629480","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:19Z","timestamp":1750249399000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629435.1629480"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,10,11]]},"references-count":21,"alternative-id":["10.1145\/1629435.1629480","10.1145\/1629435"],"URL":"https:\/\/doi.org\/10.1145\/1629435.1629480","relation":{},"subject":[],"published":{"date-parts":[[2009,10,11]]},"assertion":[{"value":"2009-10-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}