{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:16Z","timestamp":1750307536902,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,10,11]],"date-time":"2009-10-11T00:00:00Z","timestamp":1255219200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,10,11]]},"DOI":"10.1145\/1629435.1629482","type":"proceedings-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T15:11:11Z","timestamp":1255446671000},"page":"343-352","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Supporting RTL flow compatibility in a microarchitecture-level design framework"],"prefix":"10.1145","author":[{"given":"Daniel","family":"Schwartz-Narbonne","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Carven","family":"Chan","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Yogesh","family":"Mahajan","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Sharad","family":"Malik","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]}],"member":"320","published-online":{"date-parts":[[2009,10,11]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"2005","volume":"62142","author":"Transfer Level Synthesis Verilog Register","journal-title":"IEC"},{"key":"e_1_3_2_1_2_1","unstructured":"IEEE Std 1666 - 2005 IEEE Standard SystemC Language Reference Manual. IEEE Std 1666-2005 pages 1--423 2006.  IEEE Std 1666 - 2005 IEEE Standard SystemC Language Reference Manual. IEEE Std 1666-2005 pages 1--423 2006."},{"key":"e_1_3_2_1_3_1","first-page":"1","volume":"62530","author":"SystemVerilog-Unified Hardware Standard","year":"2007","journal-title":"IEC"},{"volume-title":"Proceedings. 18th International","year":"2004","author":"August D.","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/1792734.1792781"},{"key":"e_1_3_2_1_6_1","unstructured":"Cadence Design Systems. Incisive formal verifier. Online http:\/\/www.cadence.com\/ May 2009.  Cadence Design Systems. Incisive formal verifier. Online http:\/\/www.cadence.com\/ May 2009."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1333874.1334164"},{"volume-title":"Morgan Kaufmann Publishers Inc.","year":"2003","author":"Dally W.","key":"e_1_3_2_1_8_1"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.596624"},{"volume-title":"Morgan Kaufmann","year":"2006","author":"Hennessy J.","key":"e_1_3_2_1_10_1"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.833614"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/800255.810654"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2007.371235"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1333874.1334165"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2005.51"},{"key":"e_1_3_2_1_16_1","unstructured":"L.-S. Peh. Flow control and micro-architectural mechanisms for extending the performance of interconnection networks. PhD thesis 2001. Adv. William J. Dally.   L.-S. Peh. Flow control and micro-architectural mechanisms for extending the performance of interconnection networks. PhD thesis 2001. Adv. William J. Dally."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/789083.1022785"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/832284.835450"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/1015090.1015147"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146937"},{"key":"e_1_3_2_1_21_1","unstructured":"Synopsys Inc. Design compiler. Online http:\/\/www.synopsys.com May 2009.  Synopsys Inc. Design compiler. Online http:\/\/www.synopsys.com May 2009."},{"key":"e_1_3_2_1_22_1","unstructured":"S. Williams. Icarus Verilog. Online http:\/\/icarus.com\/eda\/verilog Nov. 2008.  S. Williams. Icarus Verilog. Online http:\/\/icarus.com\/eda\/verilog Nov. 2008."}],"event":{"name":"ESWeek '09: Fifth Embedded Systems Week","sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Grenoble France","acronym":"ESWeek '09"},"container-title":["Proceedings of the 7th IEEE\/ACM international conference on Hardware\/software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629435.1629482","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629435.1629482","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:19Z","timestamp":1750249399000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629435.1629482"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,10,11]]},"references-count":22,"alternative-id":["10.1145\/1629435.1629482","10.1145\/1629435"],"URL":"https:\/\/doi.org\/10.1145\/1629435.1629482","relation":{},"subject":[],"published":{"date-parts":[[2009,10,11]]},"assertion":[{"value":"2009-10-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}