{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:35:03Z","timestamp":1761647703102,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,7,26]],"date-time":"2009-07-26T00:00:00Z","timestamp":1248566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,7,26]]},"DOI":"10.1145\/1629911.1629957","type":"proceedings-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T15:11:11Z","timestamp":1255446671000},"page":"160-165","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["Resurrecting infeasible clock-gating functions"],"prefix":"10.1145","author":[{"given":"Eli","family":"Arbel","sequence":"first","affiliation":[{"name":"IBM Haifa Research Laboratory, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cindy","family":"Eisner","sequence":"additional","affiliation":[{"name":"IBM Haifa Research Laboratory, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oleg","family":"Rokhlenko","sequence":"additional","affiliation":[{"name":"IBM Haifa Research Laboratory, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,7,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1089\/106652799318274"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.335011"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/323480.323482"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278705"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996687"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391637"},{"key":"e_1_3_2_1_8_1","volume-title":"Inst. fiir Informatik","author":"Kunjan T.","year":"1997","unstructured":"T. Kunjan , U. Hinsberger , and R. Kolla . Approximative representation of Boolean functions by size controllable ROBDD's. Technical report , Inst. fiir Informatik , Univ. Wfirzburg , 1997 . T. Kunjan, U. Hinsberger, and R. Kolla. Approximative representation of Boolean functions by size controllable ROBDD's. Technical report, Inst. fiir Informatik, Univ. Wfirzburg, 1997."},{"key":"e_1_3_2_1_9_1","first-page":"230","volume-title":"Proc. of the ICCAD '08","author":"Kuo Y.","year":"2008","unstructured":"Y. Kuo , S. Weng , and S. Chang . A novel sequential circuit optimization with clock gating logic . In Proc. of the ICCAD '08 , pages 230 -- 233 , 2008 . Y. Kuo, S. Weng, and S. Chang. A novel sequential circuit optimization with clock gating logic. In Proc. of the ICCAD '08, pages 230--233, 2008."},{"key":"e_1_3_2_1_10_1","volume-title":"Synthesis and Optimization of Digital Circuits","author":"Micheli G. D.","year":"1994","unstructured":"G. D. Micheli . Synthesis and Optimization of Digital Circuits . McGraw-Hill, Inc. , 1994 . G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/646949.712733"},{"issue":"4","key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","first-page":"521","DOI":"10.3844\/jcssp.2005.521.529","article-title":"BDD path length minimization based on initial variable ordering","volume":"1","author":"Prasad P.","year":"2005","unstructured":"P. Prasad , M. Raseen , A. Assi , and S. Senanayake . BDD path length minimization based on initial variable ordering . Journal of Computer Sciences , 1 ( 4 ): 521 -- 529 , 2005 . P. Prasad, M. Raseen, A. Assi, and S. Senanayake. BDD path length minimization based on initial variable ordering. Journal of Computer Sciences, 1(4):521--529, 2005.","journal-title":"Journal of Computer Sciences"},{"issue":"103","key":"e_1_3_2_1_13_1","first-page":"415","article-title":"Clock-gating and its application to low power design of sequential circuits","volume":"47","author":"Wu Q.","year":"2000","unstructured":"Q. Wu , M. Pedram , and X. Wu . Clock-gating and its application to low power design of sequential circuits . IEEE Transactions on Computers , 47 ( 103 ): 415 -- 420 , 2000 . Q. Wu, M. Pedram, and X. Wu. Clock-gating and its application to low power design of sequential circuits. IEEE Transactions on Computers, 47(103):415--420, 2000.","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_2_1_14_1","first-page":"08","article-title":"Intelligate: scalable dynamic invariant learning for power reduction","author":"Wiener R.","year":"2008","unstructured":"R. Wiener , G. Kamhi , and M. Y. Vardi . Intelligate: scalable dynamic invariant learning for power reduction . In Proc\u00f5 of PATMOS , 08 , 2008 . R. Wiener, G. Kamhi, and M. Y. Vardi. Intelligate: scalable dynamic invariant learning for power reduction. In Proc\u00f5 of PATMOS, 08, 2008.","journal-title":"Proc\u00f5 of PATMOS"},{"key":"e_1_3_2_1_15_1","first-page":"184","volume-title":"Proc. of IFIP Int. Workshop on Logic and Architecture Synthesis","author":"Theeuwen F.","year":"1996","unstructured":"F. Theeuwen and E. Seelen . Power reduction through clock gating by symbolic manipulation . In Proc. of IFIP Int. Workshop on Logic and Architecture Synthesis , pages 184 -- 191 , 1996 . F. Theeuwen and E. Seelen. Power reduction through clock gating by symbolic manipulation. In Proc. of IFIP Int. Workshop on Logic and Architecture Synthesis, pages 184--191, 1996."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337323"},{"key":"e_1_3_2_1_17_1","first-page":"626","volume-title":"Proc. of ICCD '99","author":"Yang C.","year":"1999","unstructured":"C. Yang , V. Singhal , and M. Ciesielski . BDD decomposition for efficient logic synthesis . In Proc. of ICCD '99 , pages 626 -- 631 , 1999 . C. Yang, V. Singhal, and M. Ciesielski. BDD decomposition for efficient logic synthesis. In Proc. of ICCD '99, pages 626--631, 1999."}],"event":{"name":"DAC '09: The 46th Annual Design Automation Conference 2009","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CAS Circuits & Systems"],"location":"San Francisco California","acronym":"DAC '09"},"container-title":["Proceedings of the 46th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1629957","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629911.1629957","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:16Z","timestamp":1750249396000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1629957"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7,26]]},"references-count":17,"alternative-id":["10.1145\/1629911.1629957","10.1145\/1629911"],"URL":"https:\/\/doi.org\/10.1145\/1629911.1629957","relation":{},"subject":[],"published":{"date-parts":[[2009,7,26]]},"assertion":[{"value":"2009-07-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}