{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,9]],"date-time":"2026-02-09T10:02:36Z","timestamp":1770631356695,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":65,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,7,26]],"date-time":"2009-07-26T00:00:00Z","timestamp":1248566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,7,26]]},"DOI":"10.1145\/1629911.1629995","type":"proceedings-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T15:11:11Z","timestamp":1255446671000},"page":"304-309","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Digital VLSI logic technology using Carbon Nanotube FETs"],"prefix":"10.1145","author":[{"given":"Nishant","family":"Patil","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Albert","family":"Lin","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Zhang","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.-S. Philip","family":"Wong","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,7,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2003438"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3050345"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2005185"},{"key":"e_1_3_2_1_4_1","first-page":"1","volume-title":"Proc. IEDM","author":"Amlani I.","year":"2006","unstructured":"{Amlani 06} Amlani , I. , et al., \" First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier\" , Proc. IEDM , pp. 1 -- 4 , 2006 . {Amlani 06} Amlani, I., et al., \"First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier\", Proc. IEDM, pp. 1--4, 2006."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2007.300"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283783"},{"key":"e_1_3_2_1_7_1","volume-title":"Proc. DATE","author":"Bobba S.","year":"2009","unstructured":"{Bobba 09} Bobba , S. et al., \"Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis \", Proc. DATE , 2009 . {Bobba 09} Bobba, S. et al., \"Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis\", Proc. DATE, 2009."},{"key":"e_1_3_2_1_8_1","first-page":"015506","article-title":"Statistical circuit design with carbon nanotubes","author":"Borkar S.","year":"2007","unstructured":"{Borkar 05} Borkar , S. , et al. , \" Statistical circuit design with carbon nanotubes \", United States Patent Application 2007 015506 . {Borkar 05} Borkar, S., et al., \"Statistical circuit design with carbon nanotubes\", United States Patent Application 2007015506.","journal-title":"United States Patent Application"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature07110"},{"issue":"259","key":"e_1_3_2_1_10_1","first-page":"272","article-title":"Random Networks and Aligned Arrays of Single-Walled Carbon Nanotubes for Electronic Device Applications","volume":"1","author":"Cao Q.","year":"2008","unstructured":"{Cao 08b} Cao , Q. , and J. A. Rogers , \" Random Networks and Aligned Arrays of Single-Walled Carbon Nanotubes for Electronic Device Applications \", Nano Res , 1 : 259 272 , 2008 . {Cao 08b} Cao, Q., and J. A. Rogers, \"Random Networks and Aligned Arrays of Single-Walled Carbon Nanotubes for Electronic Device Applications\", Nano Res, 1: 259 272, 2008.","journal-title":"Nano Res"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.0837064100"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1888054"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"{Chen 06} Chen Z. etal \"An Integrated Logic Circuit Assembled on a Single Carbon Nanotube\" Science 311 (5768) 1735.  {Chen 06} Chen Z. et al. \"An Integrated Logic Circuit Assembled on a Single Carbon Nanotube\" Science 311 (5768) 1735.","DOI":"10.1126\/science.1122797"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391494"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.927373"},{"key":"e_1_3_2_1_16_1","first-page":"706","article-title":"A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors","volume":"2008","unstructured":"{Close 08b} Close G. F., , \" A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors \", Nano Letters 2008 8 (2), 706 -- 709 . {Close 08b} Close G. F., et al., \"A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors\", Nano Letters 2008 8 (2), 706--709.","journal-title":"Nano Letters"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1058782"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1021\/ar0101640"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.94"},{"key":"e_1_3_2_1_20_1","first-page":"70","volume-title":"Proc. ISSCC","author":"Deng J.","year":"2007","unstructured":"{Deng 07a} Deng , J. , et al., \" Carbon Nanotube Transistor Circuits : Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections \", Proc. ISSCC , pp. 70 -- 588 , 2007 . {Deng 07a} Deng, J., et al., \"Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections\", Proc. ISSCC, pp. 70--588, 2007."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909030"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1350763.1350767"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1021\/nn800708w"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379262"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00216-005-3400-4"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1474604"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1615\/IntJMultCompEng.v2.i2.60"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1021\/ja042544x"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/2\/017"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature01797"},{"key":"e_1_3_2_1_31_1","first-page":"31.2.1","volume-title":"Proc. IEDM","author":"Javey A., Q.","year":"2003","unstructured":"{Javey 03b} Javey , A., Q. Wang , W. Kim , H. Dai. \"Advancements in Complementary Carbon Nanotube Field-Effect Transistors\" , Proc. IEDM , pp. 31.2.1 -- 31.2.4 , 2003 . {Javey 03b} Javey, A., Q. Wang, W. Kim, H. Dai. \"Advancements in Complementary Carbon Nanotube Field-Effect Transistors\", Proc. IEDM, pp. 31.2.1--31.2.4, 2003."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl047931j"},{"key":"e_1_3_2_1_33_1","volume-title":"Carbon Nanotube Electronics","author":"Javey A.","year":"2009","unstructured":"{Javey 09} Javey , A. , and J. Kong (editors), Carbon Nanotube Electronics , Springer , 2009 . {Javey 09} Javey, A., and J. Kong (editors), Carbon Nanotube Electronics, Springer, 2009."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2007.77"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1002\/anie.200704488"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1039\/b709567h"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2108127"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2743402"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1156588"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl035097c"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2986216"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2004706"},{"key":"e_1_3_2_1_43_1","volume-title":"VLSI Tech. Symp.","author":"Lin A.","year":"2009","unstructured":"{Lin 09b} Lin , A. , et al., \" A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT)\" , to appear in Proc . VLSI Tech. Symp. , 2009 . {Lin 09b} Lin, A., et al., \"A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT)\", to appear in Proc. VLSI Tech. Symp., 2009."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.122477"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278716"},{"key":"e_1_3_2_1_46_1","first-page":"205","volume-title":"Proc. Symp. VLSI Technology","author":"Patil N.","year":"2008","unstructured":"{Patil 08a} Patil , N. , et al., \" Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube- Immune Logic Structures ,\" Proc. Symp. VLSI Technology , pp. 205 -- 206 , 2008 . {Patil 08a} Patil, N., et al., \"Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,\" Proc. Symp. VLSI Technology, pp. 205--206, 2008."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2003278"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2006903"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2016562"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl800967n"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147094"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120857"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1021\/jp0711500"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1142\/p080"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1021\/ja0169670"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/1167943.1167945"},{"key":"e_1_3_2_1_57_1","first-page":"118","volume-title":"Proc. ISSCC","author":"Tang S.","year":"2001","unstructured":"{Tang 01} Tang , S. , et al., \"Fin FET - A Quasi-Planar Double-Gate MOSFET\" , Proc. ISSCC , pp. 118 -- 119 , 2001 . {Tang 01} Tang, S., et al., \"FinFET - A Quasi-Planar Double-Gate MOSFET\", Proc. ISSCC, pp. 118--119, 2001."},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1038\/29954"},{"key":"e_1_3_2_1_59_1","first-page":"1","volume-title":"Proc. VLSI-TSA","author":"Wong S.","year":"2007","unstructured":"{Wong 07} Wong , S. , et al., \"Monolithic 3 D Integrated Circuits\" , Proc. VLSI-TSA , pp. 1 -- 4 , 2007 . {Wong 07} Wong, S., et al., \"Monolithic 3D Integrated Circuits\", Proc. VLSI-TSA, pp. 1--4, 2007."},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.73.075419"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1133781"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl0717107"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403619"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2023197"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629933"}],"event":{"name":"DAC '09: The 46th Annual Design Automation Conference 2009","location":"San Francisco California","acronym":"DAC '09","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CAS Circuits & Systems"]},"container-title":["Proceedings of the 46th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1629995","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629911.1629995","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:16Z","timestamp":1750249396000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1629995"}},"subtitle":["frequently asked questions"],"short-title":[],"issued":{"date-parts":[[2009,7,26]]},"references-count":65,"alternative-id":["10.1145\/1629911.1629995","10.1145\/1629911"],"URL":"https:\/\/doi.org\/10.1145\/1629911.1629995","relation":{},"subject":[],"published":{"date-parts":[[2009,7,26]]},"assertion":[{"value":"2009-07-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}