{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T17:32:17Z","timestamp":1764783137055,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,7,26]],"date-time":"2009-07-26T00:00:00Z","timestamp":1248566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,7,26]]},"DOI":"10.1145\/1629911.1630097","type":"proceedings-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T15:11:11Z","timestamp":1255446671000},"page":"714-719","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Fault models for embedded-DRAM macros"],"prefix":"10.1145","author":[{"given":"Mango C.-T.","family":"Chao","sequence":"first","affiliation":[{"name":"National Chiao-Tung University, Hsinchu, Taiwan"}]},{"given":"Hao-Yu","family":"Yang","sequence":"additional","affiliation":[{"name":"National Chiao-Tung University, Hsinchu, Taiwan"}]},{"given":"Rei-Fu","family":"Huang","sequence":"additional","affiliation":[{"name":"MediaTek Inc., Hsinchu, Taiwan"}]},{"given":"Shih-Chin","family":"Lin","sequence":"additional","affiliation":[{"name":"United Microelectronics Corporation, Hsinchu, Taiwan"}]},{"given":"Ching-Yu","family":"Chin","sequence":"additional","affiliation":[{"name":"National Chiao-Tung University, Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2009,7,26]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Theory and Practice,\" Gouda","author":"van de Goor A. J.","year":"1998","unstructured":"A. J. van de Goor , \" Testing Semiconductor Memories , Theory and Practice,\" Gouda , The Netherlands : ComTex , 1998 . A. J. van de Goor, \"Testing Semiconductor Memories, Theory and Practice,\" Gouda, The Netherlands: ComTex, 1998."},{"key":"e_1_3_2_1_2_1","first-page":"1","article-title":"A 0.127 &mu;m2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications","author":"Wang G.","year":"2006","unstructured":"G. Wang , , \" A 0.127 &mu;m2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications ,\" International Electron Devices Meeting, 11-- 13 Dec. 2006 , pp. 1 -- 4 . G. Wang, et al., \"A 0.127 &mu;m2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications,\" International Electron Devices Meeting, 11--13 Dec. 2006, pp. 1--4.","journal-title":"International Electron Devices Meeting, 11--"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2005.10.024"},{"key":"e_1_3_2_1_4_1","volume-title":"Quad-Density Technology Reins in Spiraling Memory Requirements,\" Mosys","author":"Jones M.-E.","year":"2007","unstructured":"M.-E. Jones , \"1T-SRAM-Q#8482; : Quad-Density Technology Reins in Spiraling Memory Requirements,\" Mosys , Inc., Retrieved on 2007 -10-06. M.-E. Jones, \"1T-SRAM-Q#8482;: Quad-Density Technology Reins in Spiraling Memory Requirements,\" Mosys, Inc., Retrieved on 2007-10-06."},{"key":"e_1_3_2_1_5_1","first-page":"343","volume-title":"Proceeding of Solid-State Device Research Conference","author":"Berthelot A.","year":"2006","unstructured":"A. Berthelot , C. Caillat , V. Huard , S. Barnola , B. Boeck , H. Del-Puppo , N. Emonet , F. Lalanne , \" Highly Reliable TiN\/ZrO2\/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies ,\" Proceeding of Solid-State Device Research Conference , Sept. 2006 , pp. 343 -- 346 . A. Berthelot, C. Caillat, V. Huard, S. Barnola, B. Boeck, H. Del-Puppo, N. Emonet, F. Lalanne, \"Highly Reliable TiN\/ZrO2\/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies,\" Proceeding of Solid-State Device Research Conference, Sept. 2006, pp. 343--346."},{"key":"e_1_3_2_1_6_1","first-page":"299","volume-title":"Yamanashi","author":"Cheng C.","year":"2000","unstructured":"C. Cheng , C.-T. Huang , J.-R. Huang , C.-W. Wu , C.-J. Wey , and M.-C. Tsai , \"BRAINS : A BIST compiler for embedded memories,\" Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , Yamanashi , Oct. 2000 , pp. 299 -- 307 . C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, \"BRAINS: A BIST compiler for embedded memories,\" Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Oct. 2000, pp. 299--307."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016557927479"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.53045"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.748806"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.466.0675"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.748805"},{"key":"e_1_3_2_1_12_1","first-page":"388","volume-title":"Digest of Technical Papers","author":"Watanabe N.","year":"2001","unstructured":"N. Watanabe , F. Morishita , Y. Taito , A. Yamazaki , T. Tanizaki , K. Dosaka , Y. Morooka , F. Igaue , K. Furue , Y. Nagura , T. Komoike , T. Morihara , A. Hachisuka , K. Arimoto , and H. Ozaki , \" An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester,\" Proceedings of the IEEE Int'l Solid-State Circuits Conference (ISSCC) , Digest of Technical Papers , 2001 , pp. 388 -- 389 . N. Watanabe, F. Morishita, Y. Taito, A. Yamazaki, T. Tanizaki, K. Dosaka, Y. Morooka, F. Igaue, K. Furue, Y. Nagura, T. Komoike, T. Morihara, A. Hachisuka, K. Arimoto, and H. Ozaki, \"An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester,\" Proceedings of the IEEE Int'l Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 2001, pp. 388--389."},{"key":"e_1_3_2_1_13_1","first-page":"128","volume-title":"1st IEEE Int'l Workshop on Electronic Design, Test and Application (DELTA 02)","author":"van de Goor A. J.","year":"2002","unstructured":"A. J. van de Goor and I. Schanstra , \" Address and Data Scrambling: Causes and Impact on Memory Tests,\" Proc . 1st IEEE Int'l Workshop on Electronic Design, Test and Application (DELTA 02) , IEEE Press , 2002 , pp. 128 -- 136 . A. J. van de Goor and I. Schanstra, \"Address and Data Scrambling: Causes and Impact on Memory Tests,\" Proc. 1st IEEE Int'l Workshop on Electronic Design, Test and Application (DELTA 02), IEEE Press, 2002, pp. 128--136."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804101"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"e_1_3_2_1_16_1","first-page":"401","volume-title":"IEEE VLSI Test Symposium","author":"Al-Ars Z.","unstructured":"Z. Al-Ars , A. J. van de Goor, \"Approximating Infinite Dynamic Behavior for DRAM Cell Defects \", IEEE VLSI Test Symposium , pp. 401 -- 406 Z. Al-Ars, A. J. van de Goor, \"Approximating Infinite Dynamic Behavior for DRAM Cell Defects\", IEEE VLSI Test Symposium, pp. 401--406"},{"key":"e_1_3_2_1_17_1","first-page":"1","volume-title":"IEEE International Test Conference","author":"Al-Ars Z.","year":"2008","unstructured":"Z. Al-Ars , S. Hamdioui , A. J. van de Goor, G. Mueller, \"Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs \", IEEE International Test Conference , pp. 1 -- 10 , 2008 . Z. Al-Ars, S. Hamdioui, A. J. van de Goor, G. Mueller, \"Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs\", IEEE International Test Conference, pp. 1--10, 2008."},{"key":"e_1_3_2_1_18_1","first-page":"433","article-title":"A forced-voltage technique to test data retention faults in CMOS SRAM by I  DDQ  testing","author":"Castillejos J.","year":"1997","unstructured":"J. Castillejos , V. H. Champac , \" A forced-voltage technique to test data retention faults in CMOS SRAM by I DDQ testing \", Circuits and Systems , pp. 433 -- 436 , 1997 . J. Castillejos, V. H. Champac, \"A forced-voltage technique to test data retention faults in CMOS SRAM by I DDQ testing\", Circuits and Systems, pp. 433--436, 1997.","journal-title":"Circuits and Systems"},{"key":"e_1_3_2_1_19_1","first-page":"1043","volume-title":"Test Conference, Proceedings.","author":"Meixner A.","year":"1997","unstructured":"A. Meixner , J. Banik , \" Weak Write Test Mode : an SRAM cell stability design for test technique \", Test Conference, Proceedings. , International , pp. 1043 -- 1052 , 1997 . A. Meixner, J. Banik, \"Weak Write Test Mode: an SRAM cell stability design for test technique\", Test Conference, Proceedings., International, pp. 1043--1052, 1997."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20000855"},{"key":"e_1_3_2_1_21_1","first-page":"78","volume-title":"IEE Proceedings","author":"Champac V. H.","year":"2004","unstructured":"V. H. Champac , V. Avendano , \"Test of data retention faults in CMOS SRAMs using special DFT circuitries\", Circuits, Devices and Systems , IEE Proceedings , pp. 78 -- 82 , 2004 . V. H. Champac, V. Avendano, \"Test of data retention faults in CMOS SRAMs using special DFT circuitries\", Circuits, Devices and Systems, IEE Proceedings, pp. 78--82, 2004."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.76"},{"key":"e_1_3_2_1_23_1","unstructured":"Electronic Industries Association and JEDEC Solid State Technology Association \"Steady State Temperature Humidity Bias Life Test \" EIA\/JESD22-A101-B April 1997.  Electronic Industries Association and JEDEC Solid State Technology Association \"Steady State Temperature Humidity Bias Life Test \" EIA\/JESD22-A101-B April 1997."},{"key":"e_1_3_2_1_24_1","unstructured":"Electronic Industries Association and JEDEC Solid State Technology Association \"Highly-Accelerated Temperature and Humidity Stress Test \" EIA\/JESD22-A110-B June 2008.  Electronic Industries Association and JEDEC Solid State Technology Association \"Highly-Accelerated Temperature and Humidity Stress Test \" EIA\/JESD22-A110-B June 2008."},{"key":"e_1_3_2_1_25_1","unstructured":"JEDEC Solid State Technology Association \"Temperature Bias and Operating Life \" JESD22-A108C June 2005.  JEDEC Solid State Technology Association \"Temperature Bias and Operating Life \" JESD22-A108C June 2005."}],"event":{"name":"DAC '09: The 46th Annual Design Automation Conference 2009","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CAS Circuits & Systems"],"location":"San Francisco California","acronym":"DAC '09"},"container-title":["Proceedings of the 46th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1630097","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629911.1630097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:21Z","timestamp":1750249401000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1630097"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7,26]]},"references-count":25,"alternative-id":["10.1145\/1629911.1630097","10.1145\/1629911"],"URL":"https:\/\/doi.org\/10.1145\/1629911.1630097","relation":{},"subject":[],"published":{"date-parts":[[2009,7,26]]},"assertion":[{"value":"2009-07-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}