{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:18Z","timestamp":1750307538733,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,7,26]],"date-time":"2009-07-26T00:00:00Z","timestamp":1248566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002338","name":"Ministry of Education of the People's Republic of China","doi-asserted-by":"publisher","award":["2.01E+11"],"award-info":[{"award-number":["2.01E+11"]}],"id":[{"id":"10.13039\/501100002338","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["6.07E+15"],"award-info":[{"award-number":["6.07E+15"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002855","name":"Ministry of Science and Technology of the People's Republic of China","doi-asserted-by":"publisher","award":["2005CB321701","8510700100"],"award-info":[{"award-number":["2005CB321701","8510700100"]}],"id":[{"id":"10.13039\/501100002855","id-type":"DOI","asserted-by":"publisher"}]},{"name":"China National Major Science and Technology","award":["2008ZX01035-001-06"],"award-info":[{"award-number":["2008ZX01035-001-06"]}]},{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS-0613967"],"award-info":[{"award-number":["CNS-0613967"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2007-HJ-1593"],"award-info":[{"award-number":["2007-HJ-1593"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,7,26]]},"DOI":"10.1145\/1629911.1630124","type":"proceedings-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T15:11:11Z","timestamp":1255446671000},"page":"832-837","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Multicore parallel min-cost flow algorithm for CAD applications"],"prefix":"10.1145","author":[{"given":"Yinghai","family":"Lu","sequence":"first","affiliation":[{"name":"Fudan University, China"}]},{"given":"Hai","family":"Zhou","sequence":"additional","affiliation":[{"name":"Northwestern University and Fudan University, China"}]},{"given":"Li","family":"Shang","sequence":"additional","affiliation":[{"name":"University of Colorado, Boulder"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"Fudan University, China"}]}],"member":"320","published-online":{"date-parts":[[2009,7,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/140901.140919"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391475"},{"key":"e_1_3_2_1_3_1","volume-title":"Parallel Program Design: A Foundation","author":"Chandy K. M.","year":"1988","unstructured":"K. M. Chandy and J. Misra . Parallel Program Design: A Foundation . Addison-Wesley Publishing Company , 1988 . K. M. Chandy and J. Misra. Parallel Program Design: A Foundation. Addison-Wesley Publishing Company, 1988."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/360933.360975"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391531"},{"key":"e_1_3_2_1_6_1","volume-title":"ISSCC","author":"J.","year":"2007","unstructured":"J. F. et al. Design of the Power6#8482; microprocessor . In ISSCC , 2007 . J. F. et al. Design of the Power6#8482; microprocessor. In ISSCC, 2007."},{"key":"e_1_3_2_1_7_1","volume-title":"ISSCC","author":"U.","year":"2007","unstructured":"U. G. et al. An 8-core 64-thread 64b power-efficient SPARC SoC . In ISSCC , 2007 . U. G. et al. An 8-core 64-thread 64b power-efficient SPARC SoC. In ISSCC, 2007."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1006\/jagm.1995.0805"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1781794.1781796"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_11_1","volume-title":"Morgan Kaufmann","author":"Herlihy M.","year":"2008","unstructured":"M. Herlihy and N. Shavit . The Art of Multiprocessor Programming . Morgan Kaufmann , 2008 . M. Herlihy and N. Shavit. The Art of Multiprocessor Programming. Morgan Kaufmann, 2008."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147023"},{"key":"e_1_3_2_1_13_1","unstructured":"Intel. Threading building blocks. http:\/\/www.threadingbuildingblocks.org\/.  Intel. Threading building blocks. http:\/\/www.threadingbuildingblocks.org\/."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1287\/mnsc.20.5.814"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1977.229904"},{"key":"e_1_3_2_1_16_1","volume-title":"Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers","author":"Lamport L.","year":"2002","unstructured":"L. Lamport . Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers . Addison-Wesley Publishing Company , 2002 . L. Lamport. Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers. Addison-Wesley Publishing Company, 2002."},{"key":"e_1_3_2_1_17_1","volume-title":"ICCAD","author":"Lee W.-P.","year":"2007","unstructured":"W.-P. Lee , H.-Y. Liu , and Y.-W. Chang . An ILP algorithm for post-floorplanning voltage-island generation considering power network planning . In ICCAD , 2007 . W.-P. Lee, H.-Y. Liu, and Y.-W. Chang. An ILP algorithm for post-floorplanning voltage-island generation considering power network planning. In ICCAD, 2007."},{"key":"e_1_3_2_1_18_1","volume-title":"ASPDAC","author":"Lin C.","year":"2007","unstructured":"C. Lin and H. Zhou . Clock skew scheduling with delay padding for prescribed skew domains . In ASPDAC , 2007 . C. Lin and H. Zhou. Clock skew scheduling with delay padding for prescribed skew domains. In ASPDAC, 2007."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233535"},{"key":"e_1_3_2_1_20_1","volume-title":"ICCAD","author":"Ma Q.","year":"2008","unstructured":"Q. Ma and E. F. Y. Young . Network flow-based power optimization under timing constraints in MSV-driven floorplanning . In ICCAD , 2008 . Q. Ma and E. F. Y. Young. Network flow-based power optimization under timing constraints in MSV-driven floorplanning. In ICCAD, 2008."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391474"},{"key":"e_1_3_2_1_22_1","unstructured":"J. B. Orlin and C. Stein. Parallel algorithms for the assignment and minimum-cost flow problems.  J. B. Orlin and C. Stein. Parallel algorithms for the assignment and minimum-cost flow problems."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/360051.360224"},{"key":"e_1_3_2_1_24_1","volume-title":"Morgan Kaufmann","author":"Pacheco P. S.","year":"1997","unstructured":"P. S. Pacheco . Parallel Programming with MPI . Morgan Kaufmann , 1997 . P. S. Pacheco. Parallel Programming with MPI. Morgan Kaufmann, 1997."},{"key":"e_1_3_2_1_25_1","volume-title":"Optimization in Operations Research","author":"Rardin R. L.","year":"1998","unstructured":"R. L. Rardin . Optimization in Operations Research . Prentice Hall , 1998 . R. L. Rardin. Optimization in Operations Research. Prentice Hall, 1998."},{"key":"e_1_3_2_1_26_1","volume-title":"Modern Processor Design: Fundamentals of Superscalar Processors","author":"Shen J. P.","year":"2005","unstructured":"J. P. Shen and M. H. Lipasti . Modern Processor Design: Fundamentals of Superscalar Processors . McGraw-Hill Professional , 2005 . J. P. Shen and M. H. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill Professional, 2005."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858266"},{"key":"e_1_3_2_1_28_1","volume-title":"ICCAD","author":"Wang J.","year":"2007","unstructured":"J. Wang , D. Das , and H. Zhou . Gate sizing by lagrangian relaxation revisited . In ICCAD , 2007 . J. Wang, D. Das, and H. Zhou. Gate sizing by lagrangian relaxation revisited. In ICCAD, 2007."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391603"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509456.1509484"}],"event":{"name":"DAC '09: The 46th Annual Design Automation Conference 2009","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CAS Circuits & Systems"],"location":"San Francisco California","acronym":"DAC '09"},"container-title":["Proceedings of the 46th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1630124","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1629911.1630124","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:21Z","timestamp":1750249401000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1629911.1630124"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7,26]]},"references-count":30,"alternative-id":["10.1145\/1629911.1630124","10.1145\/1629911"],"URL":"https:\/\/doi.org\/10.1145\/1629911.1630124","relation":{},"subject":[],"published":{"date-parts":[[2009,7,26]]},"assertion":[{"value":"2009-07-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}