{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:23Z","timestamp":1750307543045,"version":"3.41.0"},"reference-count":16,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2009,12,1]],"date-time":"2009-12-01T00:00:00Z","timestamp":1259625600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2009,12]]},"abstract":"<jats:p>Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning\/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this article, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and can simultaneously consider the tradeoff between power routing cost and total power dissipation.<\/jats:p>","DOI":"10.1145\/1640457.1640460","type":"journal-article","created":{"date-parts":[[2010,8,24]],"date-time":"2010-08-24T13:16:40Z","timestamp":1282655800000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning"],"prefix":"10.1145","volume":"15","author":[{"given":"Meng-Chen","family":"Wu","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Ming-Ching","family":"Lu","sequence":"additional","affiliation":[{"name":"SpringSoft, Inc., Hsinchu, Taiwan"}]},{"given":"Hung-Ming","family":"Chen","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Jing-Yang","family":"Jou","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2009,12,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871525"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233632"},{"volume-title":"Proceedings of the IEEE International Custom Integrated Circuits Conference (CICC). 307--310","author":"Coussy P.","key":"e_1_2_1_4_1","unstructured":"Coussy , P. , Baganne , A. , and Martin , E . 2002. A design methodology for integrating IP into SoC systems . In Proceedings of the IEEE International Custom Integrated Circuits Conference (CICC). 307--310 . Coussy, P., Baganne, A., and Martin, E. 2002. A design methodology for integrating IP into SoC systems. In Proceedings of the IEEE International Custom Integrated Circuits Conference (CICC). 307--310."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309928"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013283"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.103"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOC.2003.1241559"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774601"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233579"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.371970"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514128"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe. 996--1001","author":"Vorg A.","key":"e_1_2_1_13_1","unstructured":"Vorg , A. , Radetzki , M. , and Rosenstiel , W . 2004. measurement of IP qualification costs and benefits . In Proceedings of the Design, Automation and Test in Europe. 996--1001 . Vorg, A., Radetzki, M., and Rosenstiel, W. 2004. measurement of IP qualification costs and benefits. In Proceedings of the Design, Automation and Test in Europe. 996--1001."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/762488.762490"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 309--316","author":"Wu H.","key":"e_1_2_1_15_1","unstructured":"Wu , H. , Liu , I.-M. , Wong , M. , and Wang , Y . 2005. Post-placement voltage island generation under performance requirement . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 309--316 . Wu, H., Liu, I.-M., Wong, M., and Wang, Y. 2005. Post-placement voltage island generation under performance requirement. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 309--316."},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design. 568--571","author":"Wu M.-C.","key":"e_1_2_1_16_1","unstructured":"Wu , M.-C. and Chang , Y . -W. 2004. Placement with alignment and performance constraints using the B&ast;-tree representation . In Proceedings of the IEEE International Conference on Computer Design. 568--571 . Wu, M.-C. and Chang, Y.-W. 2004. Placement with alignment and performance constraints using the B&ast;-tree representation. In Proceedings of the IEEE International Conference on Computer Design. 568--571."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1640457.1640460","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1640457.1640460","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:26Z","timestamp":1750249406000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1640457.1640460"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12]]},"references-count":16,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2009,12]]}},"alternative-id":["10.1145\/1640457.1640460"],"URL":"https:\/\/doi.org\/10.1145\/1640457.1640460","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2009,12]]},"assertion":[{"value":"2007-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-12-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}