{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:22Z","timestamp":1750307542579,"version":"3.41.0"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2009,12,1]],"date-time":"2009-12-01T00:00:00Z","timestamp":1259625600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2009,12]]},"abstract":"<jats:p>\n            The current use of multi-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            to control leakage power targets combinational gates, even though sequential elements such as flip-flops and latches also contribute appreciable leakage. We can, nevertheless, apply multi-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            to flip-flops, but few can take advantage of high-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            , which causes abrupt changes in timing. We combine low- and high-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            at the transistor level to design mixed-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            flip-flops with reduced leakage, an unchanged footprint, and a small increase in either setup time or clock-to-Q delay, but not both. An allocation algorithm for two\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            s determines the\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            (mixed, high, or low) of each flip-flop and the\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            of each combinational gate (high or low) in a sequential circuit. Experiments with 65-nm technology show an average leakage saving of 42% compared to conventional multi-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            approaches; the leakage of flip-flops alone is cut by 78%. This saving is largely unaffected by die-to-die or within-die process variations, which we show through simulations. Standard deviation of leakage caused by process variation is also reduced due to less use of low-\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            devices. We also extend our approach to three\n            <jats:italic>\n              V\n              <jats:sub>t<\/jats:sub>\n            <\/jats:italic>\n            s, and obtain a further 14% reduction in leakage.\n          <\/jats:p>","DOI":"10.1145\/1640457.1640461","type":"journal-article","created":{"date-parts":[[2010,8,24]],"date-time":"2010-08-24T13:16:40Z","timestamp":1282655800000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Minimizing leakage power of sequential circuits through mixed-\n            <i>\n              V\n              <sub>t<\/sub>\n            <\/i>\n            flip-flops and multi-\n            <i>\n              V\n              <sub>t<\/sub>\n            <\/i>\n            combinational gates"],"prefix":"10.1145","volume":"15","author":[{"given":"Jaehyun","family":"Kim","sequence":"first","affiliation":[{"name":"Samsung Electronics, Gyeonggi-Do, Korea"}]},{"given":"Chungki","family":"Oh","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Gyeonggi-Do, Korea"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}]}],"member":"320","published-online":{"date-parts":[[2009,12,28]]},"reference":[{"volume-title":"Proceedings of the International Symposium on Circuits and Systems. 1929--1934","author":"Brglez F.","key":"e_1_2_1_1_1","unstructured":"Brglez , F. , Bryan , D. , and Kozminski , K . 1989. Combinational profiles of sequential benchmark circuits . In Proceedings of the International Symposium on Circuits and Systems. 1929--1934 . Brglez, F., Bryan, D., and Kozminski, K. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of the International Symposium on Circuits and Systems. 1929--1934."},{"key":"e_1_2_1_2_1","volume-title":"Eds","author":"Chiang C.","year":"2007","unstructured":"Chiang , C. and Kawa , J. , Eds . 2007 . Design for Manufacturability and Yield for Nano-Scale CMOS. Springer . Chiang, C. and Kawa, J., Eds. 2007. Design for Manufacturability and Yield for Nano-Scale CMOS. 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Friedrich, J., McCredie, B., James, N., Huott, B., Curran, B., Fluhr, E., Mittal, G., Chan, E., Chan, Y., Plass, D., Chu, S., Le, H., Clark, L., Ripley, J., Taylor, S., Dilullo, J., and Lanzerotti, M. 2007. Design of the Power6 microprocessor. In Proceedings of the IEEE International Solid-State Circuits Conference. 96--97."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 148--149","author":"Geissler S.","key":"e_1_2_1_8_1","unstructured":"Geissler , S. et al. 2002. A low-power RISC microprocessor using dual PLLs in a 0.13&mu;m SOI technology with copper interconnect and low-k BEOL dielectric . In Proceedings of the IEEE International Solid-State Circuits Conference. 148--149 . Geissler, S. et al. 2002. A low-power RISC microprocessor using dual PLLs in a 0.13&mu;m SOI technology with copper interconnect and low-k BEOL dielectric. In Proceedings of the IEEE International Solid-State Circuits Conference. 148--149."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857313"},{"volume-title":"Proceedings of the Asia South Pacific Design Automation Conference. 205--208","author":"Ho Y.","key":"e_1_2_1_10_1","unstructured":"Ho , Y. and Hwang , T . 2004. Low power design using dual threshold voltage . In Proceedings of the Asia South Pacific Design Automation Conference. 205--208 . Ho, Y. and Hwang, T. 2004. Low power design using dual threshold voltage. In Proceedings of the Asia South Pacific Design Automation Conference. 205--208."},{"volume-title":"Proceedings of the Custom Integrated Circuits Conference. 409--412","author":"Inukai T.","key":"e_1_2_1_11_1","unstructured":"Inukai , T. , Takamiya , M. , Nose , K. , Kawaguchi , H. , Hiramoto , T. , and Sakurai , T . 2000. Boosted gate MOS (BGMOS): device\/circuit cooperation scheme to achieve leakage-free giga-scale integration . In Proceedings of the Custom Integrated Circuits Conference. 409--412 . Inukai, T., Takamiya, M., Nose, K., Kawaguchi, H., Hiramoto, T., and Sakurai, T. 2000. Boosted gate MOS (BGMOS): device\/circuit cooperation scheme to achieve leakage-free giga-scale integration. In Proceedings of the Custom Integrated Circuits Conference. 409--412."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 274--275","author":"Ito M.","key":"e_1_2_1_12_1","unstructured":"Ito , M. et al. 2007. A 390MHz single-chip application and dual-mode baseband processor in 90nm triple-Vt CMOS . In Proceedings of the IEEE International Solid-State Circuits Conference. 274--275 . Ito, M. et al. 2007. A 390MHz single-chip application and dual-mode baseband processor in 90nm triple-Vt CMOS. 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