{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:22Z","timestamp":1750307542507,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,12,12]],"date-time":"2009-12-12T00:00:00Z","timestamp":1260576000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,12,12]]},"DOI":"10.1145\/1645213.1645227","type":"proceedings-article","created":{"date-parts":[[2009,12,15]],"date-time":"2009-12-15T12:55:59Z","timestamp":1260881759000},"page":"57-62","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["Segment gating for static energy reduction in Networks-on-Chip"],"prefix":"10.1145","author":[{"given":"Kyle C.","family":"Hale","sequence":"first","affiliation":[{"name":"The University of Texas at Austin"}]},{"given":"Boris","family":"Grot","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}]},{"given":"Stephen W.","family":"Keckler","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}]}],"member":"320","published-online":{"date-parts":[[2009,12,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871531"},{"key":"e_1_3_2_1_4_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers Inc ., San Francisco, CA, USA, 2004 . W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2004."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.140384"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812370"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874721"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.15"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871610"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601881"},{"key":"e_1_3_2_1_12_1","first-page":"55","volume-title":"Run-time Power Gating of On-Chip Routers Using Look-Ahead Routing. In Asia and South Pacific Design Automation Conference","author":"Matsutani H.","year":"2008","unstructured":"H. Matsutani , M. Koibuchi , H. Amano , and D. Wang . Run-time Power Gating of On-Chip Routers Using Look-Ahead Routing. In Asia and South Pacific Design Automation Conference , pages 55 -- 60 , January 2008 . H. Matsutani, M. Koibuchi, H. Amano, and D. Wang. Run-time Power Gating of On-Chip Routers Using Look-Ahead Routing. In Asia and South Pacific Design Automation Conference, pages 55--60, January 2008."},{"key":"e_1_3_2_1_13_1","first-page":"23","volume-title":"Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. In International Symposium on Networks-on-Chip","author":"Matsutani H.","year":"2008","unstructured":"H. Matsutani , M. Koibuchi , D. Wang , and H. Amano . Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. In International Symposium on Networks-on-Chip , pages 23 -- 32 , April 2008 . H. Matsutani, M. Koibuchi, D. Wang, and H. Amano. Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. In International Symposium on Networks-on-Chip, pages 23--32, April 2008."},{"key":"e_1_3_2_1_14_1","first-page":"151","volume-title":"Elastic-Buffer Flow Control for On-Chip Networks. In International Symposium on High-Performance Computer Architecture","author":"Michelogiannakis G.","year":"2009","unstructured":"G. Michelogiannakis , J. D. Balfour , and W. J. Dally . Elastic-Buffer Flow Control for On-Chip Networks. In International Symposium on High-Performance Computer Architecture , pages 151 -- 162 , February 2009 . G. Michelogiannakis, J. D. Balfour, and W. J. Dally. Elastic-Buffer Flow Control for On-Chip Networks. In International Symposium on High-Performance Computer Architecture, pages 151--162, February 2009."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344526"},{"key":"e_1_3_2_1_16_1","first-page":"91","volume-title":"Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In International Symposium on High-Performance Computer Architecture","author":"Shang L.","year":"2003","unstructured":"L. Shang , L.-S. Peh , and N. K. Jha . Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In International Symposium on High-Performance Computer Architecture , pages 91 -- 102 , February 2003 . L. Shang, L.-S. Peh, and N. K. Jha. Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In International Symposium on High-Performance Computer Architecture, pages 91--102, February 2003."},{"key":"e_1_3_2_1_17_1","first-page":"15","volume-title":"Peh. Dynamic Power Management for Power Optimization of Interconnection Networks Using On\/Off Links. In International Symposium on High Performance Interconnects","author":"Soteriou V.","year":"2003","unstructured":"V. Soteriou and L.- S. Peh. Dynamic Power Management for Power Optimization of Interconnection Networks Using On\/Off Links. In International Symposium on High Performance Interconnects , pages 15 -- 20 . IEEE Computer Society , August 2003 . V. Soteriou and L.-S. Peh. Dynamic Power Management for Power Optimization of Interconnection Networks Using On\/Off Links. In International Symposium on High Performance Interconnects, pages 15--20. IEEE Computer Society, August 2003."},{"key":"e_1_3_2_1_18_1","first-page":"510","volume-title":"Peh. Design-Space Exploration of Power-Aware On\/Off Interconnection Networks. In International Conference on Computer Design","author":"Soteriou V.","year":"2004","unstructured":"V. Soteriou and L.- S. Peh. Design-Space Exploration of Power-Aware On\/Off Interconnection Networks. In International Conference on Computer Design , pages 510 -- 517 , October 2004 . V. Soteriou and L.-S. Peh. Design-Space Exploration of Power-Aware On\/Off Interconnection Networks. In International Conference on Computer Design, pages 510--517, October 2004."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.43"},{"key":"e_1_3_2_1_20_1","first-page":"105","volume-title":"Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture","author":"Wang H.","year":"2003","unstructured":"H. Wang , L.-S. Peh , and S. Malik . Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture , pages 105 -- 116 , December 2003 . H. Wang, L.-S. Peh, and S. Malik. Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture, pages 105--116, December 2003."},{"key":"e_1_3_2_1_21_1","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"Weste N.","year":"2004","unstructured":"N. Weste and D. Harris . CMOS VLSI Design: A Circuits and Systems Perspective . Addison Wesley , 3 rd edition, May 2004 . N. Weste and D. Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Addison Wesley, 3rd edition, May 2004.","edition":"3"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/81.841927"}],"event":{"name":"Micro-42: The 42nd Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS TG u-Arch"],"location":"New York New York","acronym":"Micro-42"},"container-title":["Proceedings of the 2nd International Workshop on Network on Chip Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1645213.1645227","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1645213.1645227","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:25Z","timestamp":1750249405000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1645213.1645227"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12,12]]},"references-count":22,"alternative-id":["10.1145\/1645213.1645227","10.1145\/1645213"],"URL":"https:\/\/doi.org\/10.1145\/1645213.1645227","relation":{},"subject":[],"published":{"date-parts":[[2009,12,12]]},"assertion":[{"value":"2009-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}