{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:48Z","timestamp":1750307568124,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,11,15]],"date-time":"2009-11-15T00:00:00Z","timestamp":1258243200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000149","name":"Division of Engineering Education and Centers","doi-asserted-by":"publisher","award":["EEC-0642422"],"award-info":[{"award-number":["EEC-0642422"]}],"id":[{"id":"10.13039\/100000149","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,11,15]]},"DOI":"10.1145\/1646461.1646465","type":"proceedings-article","created":{"date-parts":[[2009,11,17]],"date-time":"2009-11-17T13:30:15Z","timestamp":1258464615000},"page":"29-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["A framework for core-level modeling and design of reconfigurable computing algorithms"],"prefix":"10.1145","author":[{"given":"Gongyu","family":"Wang","sequence":"first","affiliation":[{"name":"University of Florida, Gainesville, FL"}]},{"given":"Greg","family":"Stitt","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL"}]},{"given":"Herman","family":"Lam","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL"}]},{"given":"Alan D.","family":"George","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL"}]}],"member":"320","published-online":{"date-parts":[[2009,11,15]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"UK","author":"Betz V.","year":"1997","unstructured":"V. Betz , J. Rose , \"VPR : A new packing, placement and routing tool for FPGA research,\" Proc. of the 7th International Workshop on Field-Programmable Logic and Applications, London , UK , September 1997 . V. Betz, J. Rose, \"VPR: A new packing, placement and routing tool for FPGA research,\" Proc. of the 7th International Workshop on Field-Programmable Logic and Applications, London, UK, September 1997."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/581630.581670"},{"key":"e_1_3_2_1_4_1","volume-title":"Las Vegas","author":"Conger C.","year":"2008","unstructured":"C. Conger , A. Gordon-Ross , and A. George , \" FPGA Design Framework for Partial Run-Time Reconfiguration,\" Proc. of 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms , Las Vegas , Nevada , July 2008 . C. Conger, A. Gordon-Ross, and A. George, \"FPGA Design Framework for Partial Run-Time Reconfiguration,\" Proc. of 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, July 2008."},{"key":"e_1_3_2_1_5_1","volume-title":"Napa","author":"Dollas A.","year":"1998","unstructured":"A. Dollas , E. Sotiriades , and A. Emmanouelides , \" Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation,\" Proc. of the IEEE Symposium on Field-Programmable Custom Computing Machines , Napa , California , April 1998 . A. Dollas, E. Sotiriades, and A. Emmanouelides, \"Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation,\" Proc. of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 1998."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/647927.739391"},{"key":"e_1_3_2_1_7_1","volume-title":"Proc. of the IEEE, volume. 91(1)","author":"Eker J.","year":"2003","unstructured":"J. Eker , J. W. Janneck , E. A. Lee , J. Liu , X. Liu , J. Ludvig , S. Neuendorffer , S. Sachs , Y. Xiong , \"Taming Heterogeneity---the Ptolemy Approach,\" Proc. of the IEEE, volume. 91(1) , January 2003 . J. Eker, J. W. Janneck, E. A. Lee, J. Liu, X. Liu, J. Ludvig, S. Neuendorffer, S. Sachs, Y. Xiong, \"Taming Heterogeneity---the Ptolemy Approach,\" Proc. of the IEEE, volume. 91(1), January 2003."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675882"},{"key":"e_1_3_2_1_9_1","unstructured":"Floating-Point Operator v4.0 Data Sheet www.xilinx.com  Floating-Point Operator v4.0 Data Sheet www.xilinx.com"},{"key":"e_1_3_2_1_10_1","unstructured":"Floating-Point Megafunctions User Guide www. altera.com  Floating-Point Megafunctions User Guide www. altera.com"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.962304"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/330855.330988"},{"key":"e_1_3_2_1_13_1","volume-title":"Santa Fe","author":"Heysters P. M.","year":"2004","unstructured":"P. M. Heysters , G. K. Rauwerda , and G. J. M. Smit , \"Implementation of a HiperLAN\/2 receiver on the reconfigurable montium architecture,\" Proc. of the 11th Reconfigurable Architectures Workshop , Santa Fe , USA , Apirl 2004 . P. M. Heysters, G. K. Rauwerda, and G. J. M. Smit, \"Implementation of a HiperLAN\/2 receiver on the reconfigurable montium architecture,\" Proc. of the 11th Reconfigurable Architectures Workshop, Santa Fe, USA, Apirl 2004."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1328554.1328560"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1230800.1230805"},{"key":"e_1_3_2_1_16_1","volume-title":"Proc. of National Aerospace&Electronics Conference","author":"Merchant S.","year":"2008","unstructured":"S. Merchant , B. Holland , C. Reardon , A. George , H. Lam , G. Stitt , M. Smith , N. Alam , I. Gonzalez , E. El-Araby , P. Saha , T. El-Ghazawi , H. Simmler , \"Strategic Challenges for Application Development Productivity in Reconfigurable Computing,\" Proc. of National Aerospace&Electronics Conference , Dayton, OH , July 2008 . S. Merchant, B. Holland, C. Reardon, A. George, H. Lam, G. Stitt, M. Smith, N. Alam, I. Gonzalez, E. El-Araby, P. Saha, T. El-Ghazawi, H. Simmler, \"Strategic Challenges for Application Development Productivity in Reconfigurable Computing,\" Proc. of National Aerospace&Electronics Conference, Dayton, OH, July 2008."},{"key":"e_1_3_2_1_17_1","volume-title":"Automation and Test in Europe Conference and Exhibition","author":"Nayak A.","year":"2002","unstructured":"A. Nayak , M. Haldar , A. Choudhary , P. Banerjee , \"Accurate area and delay estimators for FPGAs,\" Proc. of Design , Automation and Test in Europe Conference and Exhibition , April 2002 . A. Nayak, M. Haldar, A. Choudhary, P. Banerjee, \"Accurate area and delay estimators for FPGAs,\" Proc. of Design, Automation and Test in Europe Conference and Exhibition, April 2002."},{"key":"e_1_3_2_1_18_1","volume-title":"the solution to low-power programmable DSP,\" IEEE International Conference on Acoustics, Speech, and Signal Processing","author":"Rabaey J. M.","year":"1997","unstructured":"J. M. Rabaey , \"Reconfigurable processing : the solution to low-power programmable DSP,\" IEEE International Conference on Acoustics, Speech, and Signal Processing , Munich, Germany , April 1997 . J. M. Rabaey, \"Reconfigurable processing: the solution to low-power programmable DSP,\" IEEE International Conference on Acoustics, Speech, and Signal Processing, Munich, Germany, April 1997."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258324"},{"key":"e_1_3_2_1_20_1","volume-title":"An Abstract Modeling Language for Design-Space Exploration in Reconfigurable Computing,\" submitted to IEEE Symposium on Application Specific Processors","author":"Reardon C.","year":"2009","unstructured":"C. Reardon , B. Holland , A. George , G. Stitt , H. Lam , \"RCML : An Abstract Modeling Language for Design-Space Exploration in Reconfigurable Computing,\" submitted to IEEE Symposium on Application Specific Processors , San Francisco , California , July 2009 . C. Reardon, B. Holland, A. George, G. Stitt, H. Lam, \"RCML: An Abstract Modeling Language for Design-Space Exploration in Reconfigurable Computing,\" submitted to IEEE Symposium on Application Specific Processors, San Francisco, California, July 2009."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1862648.1862655"},{"key":"e_1_3_2_1_22_1","volume-title":"Napa","author":"Sotiriades E.","year":"2000","unstructured":"E. Sotiriades , A. Dollas , and P. Athanas , \" Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine,\" Proc. of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines , Napa , California , April 2000 . E. Sotiriades, A. Dollas, and P. Athanas, \"Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine,\" Proc. of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 2000."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/512529.512550"},{"key":"e_1_3_2_1_24_1","unstructured":"D. Strenski \"FPGA Floating Point Performance -- a pencil and paper evaluation \" HPC Wire January 2007 http:\/\/www.hpcwire.com\/hpc\/1195762.html  D. Strenski \"FPGA Floating Point Performance -- a pencil and paper evaluation \" HPC Wire January 2007 http:\/\/www.hpcwire.com\/hpc\/1195762.html"},{"key":"e_1_3_2_1_25_1","volume-title":"Pipeline Vectorization for Reconfigurable Systems,\" Proc. of the 1999 IEEE Symposium on Field-Programmable Custom Computing Machines","author":"Weinhardt M.","year":"1999","unstructured":"M. Weinhardt , and W. Luk , \" Pipeline Vectorization for Reconfigurable Systems,\" Proc. of the 1999 IEEE Symposium on Field-Programmable Custom Computing Machines , Napa, California , Apirl 1999 . M. Weinhardt, and W. Luk, \"Pipeline Vectorization for Reconfigurable Systems,\" Proc. of the 1999 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, Apirl 1999."},{"key":"e_1_3_2_1_26_1","unstructured":"Xilinx System Generator for DSP User Guides Release 10.1.1 April 2008. http:\/\/www.xilinx.com\/ise\/optional_prod\/system_generator.htm  Xilinx System Generator for DSP User Guides Release 10.1.1 April 2008. http:\/\/www.xilinx.com\/ise\/optional_prod\/system_generator.htm"}],"event":{"name":"SC '09: International Conference for High Performance Computing, Networking, Storage and Analysis","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS"],"location":"Portland Oregon","acronym":"SC '09"},"container-title":["Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1646461.1646465","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1646461.1646465","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:40:57Z","timestamp":1750250457000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1646461.1646465"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11,15]]},"references-count":26,"alternative-id":["10.1145\/1646461.1646465","10.1145\/1646461"],"URL":"https:\/\/doi.org\/10.1145\/1646461.1646465","relation":{},"subject":[],"published":{"date-parts":[[2009,11,15]]},"assertion":[{"value":"2009-11-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}