{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:58:52Z","timestamp":1761580732938,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,11,14]],"date-time":"2009-11-14T00:00:00Z","timestamp":1258156800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0702341"],"award-info":[{"award-number":["CCF-0702341"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000015","name":"U.S. Department of Energy","doi-asserted-by":"publisher","award":["H98230-08-C-0272-P-3"],"award-info":[{"award-number":["H98230-08-C-0272-P-3"]}],"id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,11,14]]},"DOI":"10.1145\/1654059.1654112","type":"proceedings-article","created":{"date-parts":[[2009,11,17]],"date-time":"2009-11-17T13:30:15Z","timestamp":1258464615000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":61,"title":["Allocator implementations for network-on-chip routers"],"prefix":"10.1145","author":[{"given":"Daniel U.","family":"Becker","sequence":"first","affiliation":[{"name":"Stanford University"}]},{"given":"William J.","family":"Dally","sequence":"additional","affiliation":[{"name":"Stanford University"}]}],"member":"320","published-online":{"date-parts":[[2009,11,14]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Micheli. Networks on Chip: A New Paradigm for Systems on Chip Design. In Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02)","author":"Benini L.","year":"2002","unstructured":"L. Benini and G. de Micheli. Networks on Chip: A New Paradigm for Systems on Chip Design. In Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02) , 2002 . L. Benini and G. de Micheli. Networks on Chip: A New Paradigm for Systems on Chip Design. In Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.127260"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_4_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers , San Francisco, CA , 2004 . W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, San Francisco, CA, 2004."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/368122.369605"},{"issue":"3","key":"e_1_3_2_1_6_1","volume":"8","author":"Ford L. R.","year":"1956","unstructured":"L. R. Ford and D. R. Fulkerson . Maximal Flow through a Network. Canadian Journal of Mathematics , 8 ( 3 ), 1956 . L. R. Ford and D. R. Fulkerson. Maximal Flow through a Network. Canadian Journal of Mathematics, 8(3), 1956.","journal-title":"Maximal Flow through a Network. Canadian Journal of Mathematics"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.566196"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188554"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.1999.765457"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.15"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136487"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601881"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.769767"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605421"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006717"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2007.13"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876446"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.205650"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/800076.802479"}],"event":{"name":"SC '09: International Conference for High Performance Computing, Networking, Storage and Analysis","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS Computer Society"],"location":"Portland Oregon","acronym":"SC '09"},"container-title":["Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1654059.1654112","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1654059.1654112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:40:59Z","timestamp":1750250459000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1654059.1654112"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11,14]]},"references-count":19,"alternative-id":["10.1145\/1654059.1654112","10.1145\/1654059"],"URL":"https:\/\/doi.org\/10.1145\/1654059.1654112","relation":{},"subject":[],"published":{"date-parts":[[2009,11,14]]},"assertion":[{"value":"2009-11-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}