{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:31:28Z","timestamp":1765355488544,"version":"3.41.0"},"reference-count":32,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2010,1]]},"abstract":"<jats:p>We present three lookup-table-based AES implementations that efficiently use the BlockRAM and DSP units embedded within Xilinx Virtex-5 FPGAs. An iterative module outputs a 32-bit AES round column every clock cycle, with a throughput of 1.67 Gbit\/s when processing two 128-bit inputs. This construct is then replicated four times to provide a complete AES round per cycle with 6.7 Gbit\/s throughput when processing eight input streams. This, in turn, is replicated ten times for a fully unrolled design providing over 52 Gbit\/s of throughput. We also present implementations of a BRAM-based AES key-expansion, CMAC, and CTR modes of operation. Results for designs where DSPs are replaced by regular logic are also presented. The combination and arrangement of the specialized embedded functions available in the FPGA allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs. HDL source code, simulation testbenches, and software tool commands to reproduce reported results for the three AES variants and CMAC mode are made publicly available. Our contribution concludes with a discussion on comparing cipher implementations in the literature, and why these comparisons can be meaningless without a common reporting methodology, or within the context of a constrained target application.<\/jats:p>","DOI":"10.1145\/1661438.1661441","type":"journal-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T14:01:38Z","timestamp":1264514498000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":35,"title":["DSPs, BRAMs, and a Pinch of Logic"],"prefix":"10.1145","volume":"3","author":[{"given":"Saar","family":"Drimer","sequence":"first","affiliation":[{"name":"University of Cambridge"}]},{"given":"Tim","family":"G\u00fcneysu","sequence":"additional","affiliation":[{"name":"Ruhr University"}]},{"given":"Christof","family":"Paar","sequence":"additional","affiliation":[{"name":"Ruhr University"}]}],"member":"320","published-online":{"date-parts":[[2010,1]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"<scp>Algotronix<\/scp>. 2007. AES G3 data sheet Xilinx edition. http:\/\/www.algotronix-store.com\/kb_results.asp?ID=7.  <scp>Algotronix<\/scp>. 2007. AES G3 data sheet Xilinx edition. http:\/\/www.algotronix-store.com\/kb_results.asp?ID=7."},{"key":"e_1_2_1_2_1","volume-title":"<\/scp>","author":"Bulens P.","year":"2008","unstructured":"<scp> Bulens , P. , Standaert , F.-X. , Quisquater , J.-J. , Pellegrin , P. , and Rouvroy , G . <\/scp> 2008 . Implementation of the AES-128 on Virtex-5 FPGAs. In Proceedings of the Conference on Progress in Cryptology - AfricaCrypt. Lecture Notes in Computer Science, vol. 5023 . Springer , 16--26. <scp>Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., and Rouvroy, G.<\/scp> 2008. Implementation of the AES-128 on Virtex-5 FPGAs. In Proceedings of the Conference on Progress in Cryptology - AfricaCrypt. Lecture Notes in Computer Science, vol. 5023. Springer, 16--26."},{"volume-title":"Proceedings of the Parallel and Distributed Processing Symposium (IPDPS\u201906)","author":"Chaves R.","key":"e_1_2_1_3_1","unstructured":"<scp> Chaves , R. , Kuzmanov , G. , Vassiliadis , S. , and Sousa , L . <\/scp> 2006. Reconfigurable memory based AES co-processor . In Proceedings of the Parallel and Distributed Processing Symposium (IPDPS\u201906) . 8. <scp>Chaves, R., Kuzmanov, G., Vassiliadis, S., and Sousa, L.<\/scp> 2006. Reconfigurable memory based AES co-processor. In Proceedings of the Parallel and Distributed Processing Symposium (IPDPS\u201906). 8."},{"key":"e_1_2_1_4_1","volume-title":"<\/scp>","author":"Chodowiec P.","year":"2003","unstructured":"<scp> Chodowiec , P. and Gaj , K . <\/scp> 2003 . Very compact FPGA implementation of the AES algorithm. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), C. D. Walter, \u00c7. K. Ko\u00e7, and C. Paar, Eds. Lecture Notes in Computer Science, vol. 2779 . Springer , 319--333. <scp>Chodowiec, P. and Gaj, K.<\/scp> 2003. Very compact FPGA implementation of the AES algorithm. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), C. D. Walter, \u00c7. K. Ko\u00e7, and C. Paar, Eds. Lecture Notes in Computer Science, vol. 2779. Springer, 319--333."},{"key":"e_1_2_1_5_1","volume-title":"<\/scp>","author":"Daemen J.","year":"2002","unstructured":"<scp> Daemen , J. and Rijmen , V . <\/scp> 2002 . The Design of Rijndael: AES - The Advanced Encryption Standard. Springer . <scp>Daemen, J. and Rijmen, V.<\/scp> 2002. The Design of Rijndael: AES - The Advanced Encryption Standard. Springer."},{"key":"e_1_2_1_6_1","volume-title":"<\/scp>","author":"Dandalis A.","year":"2000","unstructured":"<scp> Dandalis , A. , Prasanna , V. , and Rolim , J . <\/scp> 2000 . A comparative study of performance of AES final candidates using FPGAs. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES). Lecture Notes in Computer Science, vol. 1965 . Springer , 125--140. <scp>Dandalis, A., Prasanna, V., and Rolim, J.<\/scp> 2000. A comparative study of performance of AES final candidates using FPGAs. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES). Lecture Notes in Computer Science, vol. 1965. Springer, 125--140."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.42"},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"<scp>Dworkin M.<\/scp> 2001. Special Publication 800-38A: Recommendation for Block Cipher Modes of Operation: Methods and Techniques. NIST.   <scp>Dworkin M.<\/scp> 2001. Special Publication 800-38A: Recommendation for Block Cipher Modes of Operation: Methods and Techniques . NIST.","DOI":"10.6028\/NIST.SP.800-38a"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"<scp>Dworkin M.<\/scp> 2005a. SP 800-38C: Recommendation for Block Cipher Modes of Operation: The CCM Mode for Authentication and Confidentiality. NIST.   <scp>Dworkin M.<\/scp> 2005a. SP 800-38C: Recommendation for Block Cipher Modes of Operation: The CCM Mode for Authentication and Confidentiality . NIST.","DOI":"10.6028\/NIST.SP.800-38b-2005"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"<scp>Dworkin M.<\/scp> 2005b. Special Publication 800-38B: Recommendation for Block Cipher Modes of Operation: The CMAC Mode for Authentication. NIST.   <scp>Dworkin M.<\/scp> 2005b. Special Publication 800-38B: Recommendation for Block Cipher Modes of Operation: The CMAC Mode for Authentication . NIST.","DOI":"10.6028\/NIST.SP.800-38b-2005"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.931230"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES\u201901)","volume":"2160","author":"Fischer V.","unstructured":"<scp> Fischer , V. and Drutarovsk\u00fd , M . <\/scp> 2001. Two methods of Rijndael implementation in reconfigurable hardware . In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES\u201901) . Lecture Notes in Computer Science , vol. 2160 . Springer, 77--92. <scp>Fischer, V. and Drutarovsk\u00fd, M.<\/scp> 2001. Two methods of Rijndael implementation in reconfigurable hardware. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES\u201901). Lecture Notes in Computer Science, vol. 2160. Springer, 77--92."},{"key":"e_1_2_1_13_1","volume-title":"<\/scp>","author":"Gaj K.","year":"2001","unstructured":"<scp> Gaj , K. and Chodowiec , P . <\/scp> 2001 . Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays. In The Cryptographers Track at the RSA Security Conference. Lecture Notes in Computer Science, vol. 2020 . Springer , 84--99. <scp>Gaj, K. and Chodowiec, P.<\/scp> 2001. Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays. In The Cryptographers Track at the RSA Security Conference. Lecture Notes in Computer Science, vol. 2020. Springer, 84--99."},{"key":"e_1_2_1_14_1","unstructured":"<scp>Gladman B.<\/scp> 2007. A specification for Rijndael the AES algorithm (version 3.16). http:\/\/gladman.plushost.co.uk\/oldsite\/cryptography_technology\/rijndael\/aes.spec.v316.pdf.  <scp>Gladman B.<\/scp> 2007. A specification for Rijndael the AES algorithm (version 3.16). http:\/\/gladman.plushost.co.uk\/oldsite\/cryptography_technology\/rijndael\/aes.spec.v316.pdf."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_31"},{"key":"e_1_2_1_16_1","unstructured":"<scp>Helion Tech.<\/scp> 2007. High performance AES (Rijndael) cores for Xilinx FPGAs. http:\/\/www.heliontech.com\/downloads\/aes_xilinx_helioncore.pdf.  <scp>Helion Tech.<\/scp> 2007. High performance AES (Rijndael) cores for Xilinx FPGAs. http:\/\/www.heliontech.com\/downloads\/aes_xilinx_helioncore.pdf."},{"volume-title":"Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u201904)","author":"Hodjat A.","key":"e_1_2_1_17_1","unstructured":"<scp> Hodjat , A. and Verbauwhede , I . <\/scp> 2004. A 21.54 Gbits\/s fully pipelined AES processor on FPGA . In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u201904) . IEEE Computer Society, 308--309. <scp>Hodjat, A. and Verbauwhede, I.<\/scp> 2004. A 21.54 Gbits\/s fully pipelined AES processor on FPGA. In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u201904). IEEE Computer Society, 308--309."},{"volume-title":"Proceedings of the AES Candidate Conference, 13--14","author":"Ichikawa T.","key":"e_1_2_1_18_1","unstructured":"<scp> Ichikawa , T. , Kasuya , T. , and Matsui , M . <\/scp> 2000. Hardware evaluation of the AES finalists . In Proceedings of the AES Candidate Conference, 13--14 . <scp>Ichikawa, T., Kasuya, T., and Matsui, M.<\/scp> 2000. Hardware evaluation of the AES finalists. In Proceedings of the AES Candidate Conference, 13--14."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611848"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/648254.752699"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/762577.2813337"},{"key":"e_1_2_1_23_1","unstructured":"<scp>NIST<\/scp> 2001. FIPS 197: Advanced Encryption Standard. NIST.  <scp>NIST<\/scp> 2001. FIPS 197: Advanced Encryption Standard . NIST."},{"key":"e_1_2_1_24_1","first-page":"583","article-title":"Compact and efficient encryption\/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications","volume":"2","author":"Rouvroy G.","year":"2004","unstructured":"<scp> Rouvroy , G. , Standaert , F.-X. , Quisquater , J.-J. , and Legat , J.-D. <\/scp> 2004 . Compact and efficient encryption\/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications . In Proceedings of the International Conference on Information Technology: Coding and Computing 2 , 583 -- 587 . <scp>Rouvroy, G., Standaert, F.-X., Quisquater, J.-J., and Legat, J.-D.<\/scp> 2004. Compact and efficient encryption\/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In Proceedings of the International Conference on Information Technology: Coding and Computing 2, 583--587.","journal-title":"Proceedings of the International Conference on Information Technology: Coding and Computing"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the International Conference on Field Progammable Logic and Applications (FPL\u201903)","volume":"2778","author":"Saggese G. P.","unstructured":"<scp> Saggese , G. P. , Mazzeo , A. , Mazzocca , N. , and Strollo , A. G. M. <\/scp> 2003. An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm . In Proceedings of the International Conference on Field Progammable Logic and Applications (FPL\u201903) , P. Y. K. Cheung, G. A. Constantinides, and J. T. de Sousa, Eds. Lecture Notes in Computer Science , vol. 2778 . Springer, 292--302. <scp>Saggese, G. P., Mazzeo, A., Mazzocca, N., and Strollo, A. G. M.<\/scp> 2003. An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In Proceedings of the International Conference on Field Progammable Logic and Applications (FPL\u201903), P. Y. K. Cheung, G. A. Constantinides, and J. T. de Sousa, Eds. Lecture Notes in Computer Science, vol. 2778. Springer, 292--302."},{"key":"e_1_2_1_26_1","unstructured":"<scp>Standaert F.-X.<\/scp> 2007. Secure and efficient implementation of symmetric encryption schemes using FPGAs. http:\/\/www.dice.ucl.ac.be\/~fstandae\/PUBLIS\/45.pdf.  <scp>Standaert F.-X.<\/scp> 2007. Secure and efficient implementation of symmetric encryption schemes using FPGAs. http:\/\/www.dice.ucl.ac.be\/~fstandae\/PUBLIS\/45.pdf."},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES\u201903)","volume":"2779","author":"Standaert F.-X.","unstructured":"<scp> Standaert , F.-X. , Rouvroy , G. , Quisquater , J.-J. , and Legat , J . -D.<\/scp> 2003. Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs . In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES\u201903) . Lecture Notes in Computer Science , vol. 2779 . Springer, 334--350. <scp>Standaert, F.-X., Rouvroy, G., Quisquater, J.-J., and Legat, J.-D.<\/scp> 2003. Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES\u201903). Lecture Notes in Computer Science, vol. 2779. Springer, 334--350."},{"key":"e_1_2_1_28_1","unstructured":"<scp>Tilera Corp.<\/scp> 2009. TILEPro64 processor. http:\/\/www.tilera.com\/products\/TILEPro64.php.  <scp>Tilera Corp.<\/scp> 2009. TILEPro64 processor. http:\/\/www.tilera.com\/products\/TILEPro64.php."},{"key":"e_1_2_1_29_1","unstructured":"<scp>Xilinx Inc.<\/scp> 2006. UG190: Virtex-5 user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug190.pdf.  <scp>Xilinx Inc.<\/scp> 2006. UG190: Virtex-5 user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug190.pdf."},{"key":"e_1_2_1_30_1","unstructured":"<scp>Xilinx Inc.<\/scp> 2007. UG193: Virtex-5 XtremeDSP design considerations user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug193.pdf.  <scp>Xilinx Inc.<\/scp> 2007. UG193: Virtex-5 XtremeDSP design considerations user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug193.pdf."},{"key":"e_1_2_1_31_1","unstructured":"<scp>Xilinx Inc.<\/scp> 2009a. Development system reference guide 10.1. http:\/\/www.xilinx.com\/itp\/xilinx10\/books\/docs\/dev\/dev.pdf.  <scp>Xilinx Inc.<\/scp> 2009a. Development system reference guide 10.1. http:\/\/www.xilinx.com\/itp\/xilinx10\/books\/docs\/dev\/dev.pdf."},{"key":"e_1_2_1_32_1","unstructured":"<scp>Xilinx Inc.<\/scp> 2009b. UG191: Virtex-5 FPGA configuration user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug191.pdf.  <scp>Xilinx Inc.<\/scp> 2009b. UG191: Virtex-5 FPGA configuration user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug191.pdf."},{"key":"e_1_2_1_33_1","unstructured":"<scp>Xilinx Inc.<\/scp> 2009c. UG440: Xilinx power estimator user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug440.pdf.  <scp>Xilinx Inc.<\/scp> 2009c. UG440: Xilinx power estimator user guide. http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug440.pdf."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1661438.1661441","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1661438.1661441","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:41:03Z","timestamp":1750250463000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1661438.1661441"}},"subtitle":["Extended Recipes for AES on FPGAs"],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":32,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2010,1]]}},"alternative-id":["10.1145\/1661438.1661441"],"URL":"https:\/\/doi.org\/10.1145\/1661438.1661441","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2010,1]]},"assertion":[{"value":"2008-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-01-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}