{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:52Z","timestamp":1750307572375,"version":"3.41.0"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000149","name":"Division of Engineering Education and Centers","doi-asserted-by":"publisher","award":["EEC-0642422"],"award-info":[{"award-number":["EEC-0642422"]}],"id":[{"id":"10.13039\/100000149","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2010,1]]},"abstract":"<jats:p>High-Level Languages (HLLs) for Field-Programmable Gate Arrays (FPGAs) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, programming at a higher level of abstraction is typically accompanied by some loss of performance as well as reduced transparency of application behavior, making it difficult to understand and improve application performance. While runtime tools for performance analysis are often featured in development with traditional HLLs for sequential and parallel programming, HLL-based development for FPGAs has an equal or greater need yet lacks these tools. This article presents a novel and portable framework for runtime performance analysis of HLL applications for FPGAs, including an automated tool for performance analysis of designs created with Impulse C, a commercial HLL for FPGAs. As a case study, this tool is used to successfully locate performance bottlenecks in a molecular dynamics kernel in order to gain speedup.<\/jats:p>","DOI":"10.1145\/1661438.1661443","type":"journal-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T14:01:38Z","timestamp":1264514498000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing"],"prefix":"10.1145","volume":"3","author":[{"given":"John","family":"Curreri","sequence":"first","affiliation":[{"name":"University of Florida"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seth","family":"Koehler","sequence":"additional","affiliation":[{"name":"University of Florida"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan D.","family":"George","sequence":"additional","affiliation":[{"name":"University of Florida"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brian","family":"Holland","sequence":"additional","affiliation":[{"name":"University of Florida"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rafael","family":"Garcia","sequence":"additional","affiliation":[{"name":"University of Florida"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,1]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1122983"},{"key":"e_1_2_1_2_1","unstructured":"Altera. 2007. Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform. http:\/\/www.altera.com\/literature\/wp\/wp-01035.pdf. Altera . 2007. Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform. http:\/\/www.altera.com\/literature\/wp\/wp-01035.pdf."},{"key":"e_1_2_1_3_1","unstructured":"Altera. 2008. Design debugging using the SignalTap II embedded logic analyzer. http:\/\/www.altera.com\/literature\/hb\/qts\/qts_qii53009.pdf. Altera . 2008. Design debugging using the SignalTap II embedded logic analyzer. http:\/\/www.altera.com\/literature\/hb\/qts\/qts_qii53009.pdf."},{"volume-title":"Proceedings of the International Conference on Computer Design (ICCD): VLSI in Computers and Processors. 2--4.","author":"Calvez J. P.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.18"},{"volume-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). 175--181","author":"DeVille R.","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1058426.1058867"},{"volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 228--237","author":"Hemmert K. S.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","first-page":"1","article-title":"IEEE standard test access port and boundary-scan architecture","volume":"1149","author":"IEEE Computer Society","year":"2001","journal-title":"IEEE Std"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2008.01.008"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1015789220266"},{"volume":"2790","volume-title":"Proceedings of the European Conference on Parallel Computing (EuroPar). Lecture Notes in Computer Science","author":"Mohr B.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1369396.1369398"},{"key":"e_1_2_1_14_1","unstructured":"Pellerin D. 2007. Email transaction on adding comments to HDL for HLL source correlation. Dec 2007. Pellerin D. 2007. Email transaction on adding comments to HDL for HLL source correlation. Dec 2007."},{"key":"e_1_2_1_15_1","unstructured":"Pellerin D. and Thibault S. 2005. Practical FPGA Programming in C. Prentice Hall PTR. Pellerin D. and Thibault S. 2005. Practical FPGA Programming in C . Prentice Hall PTR."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.110"},{"volume-title":"Proceedings of the 9th IEEE International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC). 14--15","author":"Su H.","key":"e_1_2_1_17_1"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1062261.1062284"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342006064482"},{"volume-title":"Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECE). 1687--1690","author":"Tong J. G.","key":"e_1_2_1_20_1"},{"key":"e_1_2_1_21_1","unstructured":"Xilinx. 2007. Xilinx ChipScope Pro software and cores user guide v. 9.2i. http:\/\/www.xilinx.com\/ise\/verification\/chipscope_pro_sw_cores_9_2i_ug029.pdf. Xilinx . 2007. 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