{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,22]],"date-time":"2025-10-22T05:11:56Z","timestamp":1761109916952,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,12,12]],"date-time":"2009-12-12T00:00:00Z","timestamp":1260576000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,12,12]]},"DOI":"10.1145\/1669112.1669126","type":"proceedings-article","created":{"date-parts":[[2009,12,21]],"date-time":"2009-12-21T15:04:58Z","timestamp":1261407898000},"page":"89-99","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":124,"title":["Improving cache lifetime reliability at ultra-low voltages"],"prefix":"10.1145","author":[{"given":"Zeshan","family":"Chishti","sequence":"first","affiliation":[{"name":"Oregon Microarchitecture Research, Intel Labs"}]},{"given":"Alaa R.","family":"Alameldeen","sequence":"additional","affiliation":[{"name":"Oregon Microarchitecture Research, Intel Labs"}]},{"given":"Chris","family":"Wilkerson","sequence":"additional","affiliation":[{"name":"Oregon Microarchitecture Research, Intel Labs"}]},{"given":"Wei","family":"Wu","sequence":"additional","affiliation":[{"name":"Oregon Microarchitecture Research, Intel Labs"}]},{"given":"Shih-Lien","family":"Lu","sequence":"additional","affiliation":[{"name":"Oregon Microarchitecture Research, Intel Labs"}]}],"member":"320","published-online":{"date-parts":[[2009,12,12]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"655","article-title":"Erratic Fluctuations of SRAM Cache Vmin at the 90nm Process Technology Node","author":"Agostinelli M.","year":"2005","unstructured":"M. Agostinelli , , \" Erratic Fluctuations of SRAM Cache Vmin at the 90nm Process Technology Node ,\" IEDM Technical Digest , pp. 655 -- 658 , Dec 2005 . M. Agostinelli, et al., \"Erratic Fluctuations of SRAM Cache Vmin at the 90nm Process Technology Node,\" IEDM Technical Digest, pp. 655--658, Dec 2005.","journal-title":"IEDM Technical Digest"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320111"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"e_1_3_2_1_6_1","volume-title":"DSN 2007 Workshop on Dependable and Secure Nanocomputing","author":"Constantinescu C.","year":"2007","unstructured":"C. Constantinescu , \" Impact of Intermittent Faults on Nanocomputing Devices\" DSN 2007 Workshop on Dependable and Secure Nanocomputing , June , 2007 . C. Constantinescu, \"Impact of Intermittent Faults on Nanocomputing Devices\" DSN 2007 Workshop on Dependable and Secure Nanocomputing, June, 2007."},{"key":"e_1_3_2_1_7_1","volume-title":"Proc. 18th IEEE Symposium on High-Performance Chips","author":"Doweck J.","year":"2006","unstructured":"J. Doweck , \" Inside the Core#8482; Microarchitecture ,\" Proc. 18th IEEE Symposium on High-Performance Chips , August , 2006 . J. Doweck, \"Inside the Core#8482; Microarchitecture,\" Proc. 18th IEEE Symposium on High-Performance Chips, August, 2006."},{"key":"e_1_3_2_1_8_1","first-page":"73","article-title":"Impact of CMOS Scaling and SOI on Soft Error Rates of Logic Processes","author":"Hareland S.","year":"2001","unstructured":"S. Hareland , , \" Impact of CMOS Scaling and SOI on Soft Error Rates of Logic Processes ,\" VLSI Technology Digest of Technical Papers , pp. 73 -- 74 , 2001 . S. Hareland, et al., \"Impact of CMOS Scaling and SOI on Soft Error Rates of Logic Processes,\" VLSI Technology Digest of Technical Papers, pp. 73--74, 2001.","journal-title":"VLSI Technology Digest of Technical Papers"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0390"},{"key":"e_1_3_2_1_10_1","first-page":"492","volume-title":"Proceedings of the 2007 IEEE International Solid State Circuits Conference.","author":"Ihm J.","unstructured":"J. Ihm , An 80nm 4Gb\/s\/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion .\" Proceedings of the 2007 IEEE International Solid State Circuits Conference. pp. 492 -- 493 . J. Ihm, et al., \"An 80nm 4Gb\/s\/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.\" Proceedings of the 2007 IEEE International Solid State Circuits Conference. pp. 492--493."},{"key":"e_1_3_2_1_11_1","unstructured":"Intel Corporation \"Intel\u00ae Celeron\u00ae Processor -- Low Power\/Ultra Low Power \" October 2001 http:\/\/download.intel.com\/design\/intarch\/datashts\/27350901.pdf.  Intel Corporation \"Intel\u00ae Celeron\u00ae Processor -- Low Power\/Ultra Low Power \" October 2001 http:\/\/download.intel.com\/design\/intarch\/datashts\/27350901.pdf."},{"key":"e_1_3_2_1_12_1","first-page":"324","volume-title":"Symposium On VLSI Circuits Digest of Technical Papers","author":"Karnik T.","year":"2004","unstructured":"T. Karnik , Impact of Body Bias on Alpha- and Neutron-Induced Soft Error Rates of Flip_flops,\" Symposium On VLSI Circuits Digest of Technical Papers , pp. 324 -- 325 , 2004 . T. Karnik, et al., \"Impact of Body Bias on Alpha- and Neutron-Induced Soft Error Rates of Flip_flops,\" Symposium On VLSI Circuits Digest of Technical Papers, pp. 324--325, 2004."},{"key":"e_1_3_2_1_13_1","first-page":"945","volume-title":"IEEE International Electron Devices Meeting","author":"Kawakami Y.","year":"2004","unstructured":"Y. Kawakami , Investigation of Soft Error Rate Including Multi-Bit Upsets in Advanced SRAM using Neutron Irradiation Test and 3 D Mixed-Mode Device Simulation ,\" IEEE International Electron Devices Meeting , pp. 945 -- 948 , Dec. 2004 . Y. Kawakami, et al., \"Investigation of Soft Error Rate Including Multi-Bit Upsets in Advanced SRAM using Neutron Irradiation Test and 3D Mixed-Mode Device Simulation,\" IEEE International Electron Devices Meeting, pp. 945--948, Dec. 2004."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331719"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"e_1_3_2_1_16_1","volume-title":"Proc. 1st Workshop on the System Effects of Logic Soft Errors (SELSE)","author":"Li X.","year":"2005","unstructured":"X. Li , Scaling of Architecture Level Soft Error Rates for Superscalar Processors ,\" Proc. 1st Workshop on the System Effects of Logic Soft Errors (SELSE) , April 2005 . X. Li, et al., \"Scaling of Architecture Level Soft Error Rates for Superscalar Processors,\" Proc. 1st Workshop on the System Effects of Logic Soft Errors (SELSE), April 2005."},{"key":"e_1_3_2_1_17_1","volume-title":"Error Control Coding","author":"Lin S.","year":"2004","unstructured":"S. Lin and D. J. Costello , \" Error Control Coding ,\" Second Edition. Prentice-Hall, Inc. , Upper Saddle River, NJ, USA, 2004 . S. Lin and D. J. Costello, \"Error Control Coding,\" Second Edition. Prentice-Hall, Inc., Upper Saddle River, NJ, USA, 2004."},{"key":"e_1_3_2_1_18_1","first-page":"248","volume-title":"IEEE Workshop on Signal Processing Systems (SIPS)","author":"Liu W.","year":"2006","unstructured":"W. Liu , J. Rho , and W. Sung , \" Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories,\" in Proc . IEEE Workshop on Signal Processing Systems (SIPS) , Banff , 2006 , pp. 248 -- 253 . W. Liu, J. Rho, and W. Sung, \"Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories,\" in Proc. IEEE Workshop on Signal Processing Systems (SIPS), Banff, 2006, pp. 248--253."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.37"},{"key":"e_1_3_2_1_20_1","first-page":"144","article-title":"A 50% Noise Reduction Interface Using Low-Weight Coding","author":"Nakamura K.","year":"1996","unstructured":"K. Nakamura , and M. Horowitz , \" A 50% Noise Reduction Interface Using Low-Weight Coding ,\" Symposium on VLSI Circuits Digest of Technical Papers , pp. 144 -- 145 , June 1996 . K. Nakamura, and M. Horowitz, \"A 50% Noise Reduction Interface Using Low-Weight Coding,\" Symposium on VLSI Circuits Digest of Technical Papers, pp. 144--145, June 1996.","journal-title":"Symposium on VLSI Circuits Digest of Technical Papers"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/1302494.1302862"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2007.60"},{"key":"e_1_3_2_1_23_1","first-page":"314","volume-title":"Proceedings of the 2007 IEEE International Solid State Circuits Conference","author":"Schinkel D.","unstructured":"D. Schinkel , A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup + Hold Time .\" Proceedings of the 2007 IEEE International Solid State Circuits Conference , pp. 314 -- 315 . D. Schinkel, et al., \"A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup + Hold Time.\" Proceedings of the 2007 IEEE International Solid State Circuits Conference, pp. 314--315."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051122"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/647883.738394"},{"key":"e_1_3_2_1_26_1","first-page":"276","volume-title":"Proc. 31st International Symposium on Computer Architecture (ISCA '04)","author":"Srinivasan J.","year":"2004","unstructured":"J. Srinivasan , The Case for Lifetime Reliability-Aware Microprocessors ,\" Proc. 31st International Symposium on Computer Architecture (ISCA '04) , pp. 276 -- 287 , June 2004 . J. Srinivasan, et al., \"The Case for Lifetime Reliability-Aware Microprocessors,\" Proc. 31st International Symposium on Computer Architecture (ISCA '04), pp. 276--287, June 2004."},{"key":"e_1_3_2_1_27_1","first-page":"144","volume-title":"Fundamentals of Modern VLSI Devices,\" Cambridge University Press","author":"Taur Y.","year":"1998","unstructured":"Y. Taur and T. H. Ning , \" Fundamentals of Modern VLSI Devices,\" Cambridge University Press , 1998 , pp. 144 . Y. Taur and T. H. Ning, \"Fundamentals of Modern VLSI Devices,\" Cambridge University Press, 1998, pp. 144."},{"key":"e_1_3_2_1_28_1","unstructured":"TSMC standard cell libraries. http:\/\/www.cadence.com\/partners\/tsmc\/SC_Brochure_9.pdf  TSMC standard cell libraries. http:\/\/www.cadence.com\/partners\/tsmc\/SC_Brochure_9.pdf"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.nima.2007.04.049"},{"key":"e_1_3_2_1_30_1","first-page":"264","volume-title":"31st International Symposium on Computer Architecture (ISCA-31)","author":"Weaver C.","year":"2004","unstructured":"C. Weaver , Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor,\" Proc . 31st International Symposium on Computer Architecture (ISCA-31) , pp. 264 -- 275 , June 2004 . C. Weaver, et al., \"Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor,\" Proc. 31st International Symposium on Computer Architecture (ISCA-31), pp. 264--275, June 2004."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"e_1_3_2_1_32_1","volume-title":"IEEE\/ACM Asian-South Pacific Design Automation Conference (ASPDAC)","author":"Wu K.","year":"2008","unstructured":"K. Wu and D. Marculescu , \" Soft Error Rate Reduction Using Redundancy Addition and Removal,\" in Proc . IEEE\/ACM Asian-South Pacific Design Automation Conference (ASPDAC) , Seoul, Korea , Jan. 2008 K. Wu and D. Marculescu, \"Soft Error Rate Reduction Using Redundancy Addition and Removal,\" in Proc. IEEE\/ACM Asian-South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.401.0051"}],"event":{"name":"Micro-42: The 42nd Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS TG u-Arch"],"location":"New York New York","acronym":"Micro-42"},"container-title":["Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1669112.1669126","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1669112.1669126","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:18:03Z","timestamp":1750249083000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1669112.1669126"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12,12]]},"references-count":33,"alternative-id":["10.1145\/1669112.1669126","10.1145\/1669112"],"URL":"https:\/\/doi.org\/10.1145\/1669112.1669126","relation":{},"subject":[],"published":{"date-parts":[[2009,12,12]]},"assertion":[{"value":"2009-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}