{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T13:00:38Z","timestamp":1773406838377,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":35,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,12,12]],"date-time":"2009-12-12T00:00:00Z","timestamp":1260576000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0702617CNS-0916887CCF-0903432"],"award-info":[{"award-number":["CCF-0702617CNS-0916887CCF-0903432"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CCF-0702617CNS-0916887CCF-0903432"],"award-info":[{"award-number":["CCF-0702617CNS-0916887CCF-0903432"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,12,12]]},"DOI":"10.1145\/1669112.1669151","type":"proceedings-article","created":{"date-parts":[[2009,12,21]],"date-time":"2009-12-21T15:04:58Z","timestamp":1261407898000},"page":"292-303","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":90,"title":["A case for dynamic frequency tuning in on-chip networks"],"prefix":"10.1145","author":[{"given":"Asit K.","family":"Mishra","sequence":"first","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Reetuparna","family":"Das","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Soumya","family":"Eachempati","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}]},{"given":"N.","family":"Vijaykrishnan","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]}],"member":"320","published-online":{"date-parts":[[2009,12,12]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"65\n    nm PTM Technology Model http:\/\/www.eas.asu.edu\/ptm\/.  65 nm PTM Technology Model http:\/\/www.eas.asu.edu\/ptm\/."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_3_1","volume-title":"Special Session at ISLPED","author":"Borkar S.","year":"2007"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"e_1_3_2_1_5_1","volume-title":"Dynamic Thermal Management for High-Performance Microprocessors. In 7th Intl. Symp. High Performance Computer Architecture","author":"Brooks D.","year":"2001"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658641"},{"key":"e_1_3_2_1_7_1","first-page":"141","volume-title":"Symposium on High Performance Interconnects (Hot Interconnects)","author":"Galles M.","year":"1996"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658640"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.114"},{"key":"e_1_3_2_1_10_1","unstructured":"K. Hausman G. Gaudenzi J. Mosley and S. Tempest. US Patent 4978927 - Programmable Voltage Controlled Ring Oscillator. 1990.  K. Hausman G. Gaudenzi J. Mosley and S. Tempest. US Patent 4978927 - Programmable Voltage Controlled Ring Oscillator. 1990."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/1320302.1320837"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.86"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.19"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1095890.1095915"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065726"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.25"},{"key":"e_1_3_2_1_17_1","volume-title":"Per-Core DVFS Using On-Chip Switching Regulators. In Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA)","author":"Kim W.","year":"2008"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601881"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.37"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.27"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"e_1_3_2_1_23_1","volume-title":"Low-Latency Virtual-Channel Routers for On-Chip Networks. In ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture","author":"Mullins R.","year":"2004"},{"key":"e_1_3_2_1_24_1","volume-title":"3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2)","author":"Muralimanohar N.","year":"2006"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250708"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876446"},{"key":"e_1_3_2_1_27_1","volume-title":"Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In 8th Intl. Symp. on High-Performance Computer Arch.","author":"Semeraro G.","year":"2002"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782830"},{"key":"e_1_3_2_1_29_1","volume-title":"Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In 9th Int. Symp. High Performance Computer Architecture","author":"Shang L.","year":"2003"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.35"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825121"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250703"},{"key":"e_1_3_2_1_33_1","volume-title":"CMOS. In IEEE International Solid-State Circuits Conference, ISSCC","author":"Vangal S.","year":"2007"},{"key":"e_1_3_2_1_34_1","volume-title":"ACM\/IEEE MICRO","author":"Wang H.","year":"2002"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781138"}],"event":{"name":"Micro-42: The 42nd Annual IEEE\/ACM International Symposium on Microarchitecture","location":"New York New York","acronym":"Micro-42","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS TG u-Arch"]},"container-title":["Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1669112.1669151","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1669112.1669151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:40:57Z","timestamp":1750250457000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1669112.1669151"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12,12]]},"references-count":35,"alternative-id":["10.1145\/1669112.1669151","10.1145\/1669112"],"URL":"https:\/\/doi.org\/10.1145\/1669112.1669151","relation":{},"subject":[],"published":{"date-parts":[[2009,12,12]]},"assertion":[{"value":"2009-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}