{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T10:03:45Z","timestamp":1781258625580,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,12,12]],"date-time":"2009-12-12T00:00:00Z","timestamp":1260576000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,12,12]]},"DOI":"10.1145\/1669112.1669165","type":"proceedings-article","created":{"date-parts":[[2009,12,21]],"date-time":"2009-12-21T15:04:58Z","timestamp":1261407898000},"page":"413-422","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":83,"title":["Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems"],"prefix":"10.1145","author":[{"given":"Daniel","family":"Hackenberg","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel","family":"Molka","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wolfgang E.","family":"Nagel","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2009,12,12]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"CPU2006 published results page: http:\/\/www.spec.org\/cpu2006\/results\/.","author":"SPEC","unstructured":"SPEC CPU2006 published results page: http:\/\/www.spec.org\/cpu2006\/results\/. SPEC CPU2006 published results page: http:\/\/www.spec.org\/cpu2006\/results\/."},{"key":"e_1_3_2_1_2_1","volume-title":"September","author":"AMD.","year":"2007","unstructured":"AMD. AMD64 Architecture Programmer's Manual Volume 2: System Programming, revision: 3.14 edition , September 2007 . Publication # 24593. AMD. AMD64 Architecture Programmer's Manual Volume 2: System Programming, revision: 3.14 edition, September 2007. Publication # 24593."},{"key":"e_1_3_2_1_3_1","volume-title":"September","author":"Software Optimization Guide AMD.","year":"2007","unstructured":"AMD. Software Optimization Guide For AMD Family 10h Processors , revision: 3.04 edition , September 2007 . Publication # 40546. AMD. Software Optimization Guide For AMD Family 10h Processors, revision: 3.04 edition, September 2007. Publication # 40546."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-93799-9_5"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.43"},{"key":"e_1_3_2_1_6_1","first-page":"102","volume-title":"IEEE International Solid-State Circuits Conference","author":"Dorsey J.","year":"2007","unstructured":"J. Dorsey , S. Searles , M. Ciraula , S. Johnson , N. Bujanos , D. Wu , M. Braganza , S. Meyers , E. Fang , and R. Kumar . An integrated quad-core opteron processor . In IEEE International Solid-State Circuits Conference , pages 102 -- 103 , 2007 . J. Dorsey, S. Searles, M. Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, and R. Kumar. An integrated quad-core opteron processor. In IEEE International Solid-State Circuits Conference, pages 102--103, 2007."},{"key":"e_1_3_2_1_7_1","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy J. L.","year":"2006","unstructured":"J. L. Hennessy and D. A. Patterson . Computer Architecture: A Quantitative Approach . Fourth edition, 2006 . J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Fourth edition, 2006."},{"key":"e_1_3_2_1_8_1","volume-title":"March","year":"2009","unstructured":"Intel. Intel 64 and IA-32 Architectures Optimization Reference Manual , March 2009 . Intel. Intel 64 and IA-32 Architectures Optimization Reference Manual, March 2009."},{"key":"e_1_3_2_1_9_1","volume-title":"January","year":"2009","unstructured":"Intel. An Introduction to the Intel QuickPath Interconnect , January 2009 . Intel. An Introduction to the Intel QuickPath Interconnect, January 2009."},{"key":"e_1_3_2_1_10_1","first-page":"501","volume-title":"PARCO","author":"Juckeland G.","year":"2003","unstructured":"G. Juckeland , S. B\u00f6rner , M. Kluge , S. K\u00f6lling , W. E. Nagel , S. Pfl\u00fcger , and H. R\u00f6ding . BenchIT - performance measurements and comparison for scientific applications . In PARCO , pages 501 -- 508 , 2003 . G. Juckeland, S. B\u00f6rner, M. Kluge, S. K\u00f6lling, W. E. Nagel, S. Pfl\u00fcger, and H. R\u00f6ding. BenchIT - performance measurements and comparison for scientific applications. In PARCO, pages 501--508, 2003."},{"key":"e_1_3_2_1_11_1","first-page":"19","volume-title":"IEEE Computer Society Technical Committee on Computer Architecture Newsletter","author":"McCalpin J. D.","year":"1995","unstructured":"J. D. McCalpin . Memory bandwidth and machine balance in current high performance computers . IEEE Computer Society Technical Committee on Computer Architecture Newsletter , pages 19 -- 25 , December 1995 . J. D. McCalpin. Memory bandwidth and machine balance in current high performance computers. IEEE Computer Society Technical Committee on Computer Architecture Newsletter, pages 19--25, December 1995."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.02.004"}],"event":{"name":"Micro-42: The 42nd Annual IEEE\/ACM International Symposium on Microarchitecture","location":"New York New York","acronym":"Micro-42","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS TG u-Arch"]},"container-title":["Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1669112.1669165","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1669112.1669165","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:40:57Z","timestamp":1750250457000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1669112.1669165"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12,12]]},"references-count":12,"alternative-id":["10.1145\/1669112.1669165","10.1145\/1669112"],"URL":"https:\/\/doi.org\/10.1145\/1669112.1669165","relation":{},"subject":[],"published":{"date-parts":[[2009,12,12]]},"assertion":[{"value":"2009-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}