{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:31Z","timestamp":1750308811809,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2009,11,2]],"date-time":"2009-11-02T00:00:00Z","timestamp":1257120000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2009,11,2]]},"DOI":"10.1145\/1687399.1687471","type":"proceedings-article","created":{"date-parts":[[2010,1,5]],"date-time":"2010-01-05T15:05:14Z","timestamp":1262703914000},"page":"375-380","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Retiming and time borrowing"],"prefix":"10.1145","author":[{"given":"Seonggwan","family":"Lee","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seungwhun","family":"Paik","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2009,11,2]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Closing the Gap Between ASIC & Custom","author":"Chinnery D.","year":"2002","unstructured":"D. Chinnery and K. Keutzer , Closing the Gap Between ASIC & Custom , Kluwer Academic Publishers , 2002 . D. Chinnery and K. Keutzer, Closing the Gap Between ASIC & Custom, Kluwer Academic Publishers, 2002."},{"key":"e_1_3_2_1_2_1","first-page":"138","volume-title":"IEEE Int. Solid-State Circuits Conf.","author":"Partovi H.","year":"1996","unstructured":"H. Partovi latch and edge-triggered flip-flop hybrid elements,\" in Proc . IEEE Int. Solid-State Circuits Conf. , Feb. 1996 , pp. 138 -- 139 . H. Partovi et al., \"Flow-through latch and edge-triggered flip-flop hybrid elements,\" in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 138--139."},{"key":"e_1_3_2_1_3_1","first-page":"140","volume-title":"IEEE Int. Solid-State Circuits Conf.","author":"Kozu S.","year":"1996","unstructured":"S. Kozu A 100 MHz 0.4W RISC processor with 200 MHz multiply-adder, using pulse-register technique,\" in Proc . IEEE Int. Solid-State Circuits Conf. , Feb. 1996 , pp. 140 -- 141 . S. Kozu et al., \"A 100 MHz 0.4W RISC processor with 200 MHz multiply-adder, using pulse-register technique,\" in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 140--141."},{"key":"e_1_3_2_1_4_1","first-page":"94","volume-title":"IEEE Int. Solid-State Circuits Conf.","author":"Scherer A.","year":"1999","unstructured":"A. Scherer out-of-order three-way superscalar multimedia floating-point unit,\" in Proc . IEEE Int. Solid-State Circuits Conf. , Feb. 1999 , pp. 94 -- 95 . A. Scherer et al., \"An out-of-order three-way superscalar multimedia floating-point unit,\" in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1999, pp. 94--95."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.962279"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.962284"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803943"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818146"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"issue":"3","key":"e_1_3_2_1_10_1","first-page":"12","article-title":"Chip clocking effect on performance for IBM's SA-27E ASIC technology","volume":"6","author":"Carrig K.","year":"2000","unstructured":"K. Carrig , \" Chip clocking effect on performance for IBM's SA-27E ASIC technology ,\" IBM Micronews , vol. 6 , no. 3 , pp. 12 -- 16 , 2000 . K. Carrig, \"Chip clocking effect on performance for IBM's SA-27E ASIC technology,\" IBM Micronews, vol. 6, no. 3, pp. 12--16, 2000.","journal-title":"IBM Micronews"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009896"},{"key":"e_1_3_2_1_12_1","first-page":"224","volume-title":"Int. Conf. on Computer-Aided Design","author":"Lee H.","year":"2008","unstructured":"H. Lee , S. Paik , and Y. Shin , \" Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits,\" in Proc . Int. Conf. on Computer-Aided Design , Nov. 2008 , pp. 224 -- 229 . H. Lee, S. Paik, and Y. Shin, \"Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits,\" in Proc. Int. Conf. on Computer-Aided Design, Nov. 2008, pp. 224--229."},{"key":"e_1_3_2_1_13_1","volume-title":"Design for Manufacturability and Yield for Nano-Scale CMOS","author":"Chiang C.","year":"2007","unstructured":"C. Chiang and J. Kawa , Design for Manufacturability and Yield for Nano-Scale CMOS , Springer , 2007 . C. Chiang and J. Kawa, Design for Manufacturability and Yield for Nano-Scale CMOS, Springer, 2007."},{"key":"e_1_3_2_1_14_1","first-page":"23","volume-title":"CalTech Conf. on VLSI","author":"Leiserson C.","year":"1983","unstructured":"C. Leiserson , F. Rose , and J. Saxe , \" Optimizing synchronous circuitry by retiming,\" in Proc . CalTech Conf. on VLSI , Mar. 1983 , pp. 23 -- 36 . C. Leiserson, F. Rose, and J. Saxe, \"Optimizing synchronous circuitry by retiming,\" in Proc. CalTech Conf. on VLSI, Mar. 1983, pp. 23--36."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.541443"},{"key":"e_1_3_2_1_16_1","volume-title":"Timing","author":"Sapatnekar S.","year":"2004","unstructured":"S. Sapatnekar , Timing , Kluwer Academic Publishers , 2004 . S. Sapatnekar, Timing, Kluwer Academic Publishers, 2004."},{"issue":"1","key":"e_1_3_2_1_17_1","first-page":"6","article-title":"Retiming synchronous circuitry","volume":"6","author":"Leiserson C.","year":"1991","unstructured":"C. Leiserson and J. Saxe , \" Retiming synchronous circuitry ,\" Algorithmica , vol. 6 , no. 1 -- 6 , pp. 5--35, June 1991 . C. Leiserson and J. Saxe, \"Retiming synchronous circuitry,\" Algorithmica, vol. 6, no. 1--6, pp. 5--35, June 1991.","journal-title":"Algorithmica"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503067"},{"key":"e_1_3_2_1_19_1","first-page":"533","volume-title":"Asia-Pacific Conf. on Circuits and Systems","author":"Kohira Y.","year":"2004","unstructured":"Y. Kohira and A. Takahashi , \" Clock period minimization method of semi-synchronous circuits by delay insertion,\" in Proc . Asia-Pacific Conf. on Circuits and Systems , Dec. 2004 , pp. 533 -- 536 . Y. Kohira and A. Takahashi, \"Clock period minimization method of semi-synchronous circuits by delay insertion,\" in Proc. Asia-Pacific Conf. on Circuits and Systems, Dec. 2004, pp. 533--536."},{"key":"e_1_3_2_1_20_1","first-page":"541","volume-title":"Asia South Pacific Design Automation Conf.","author":"Lin C.","year":"2007","unstructured":"C. Lin and H. Zhou , \" Clock skew scheduling with delay padding for prescribed skew domains,\" in Proc . Asia South Pacific Design Automation Conf. , Jan. 2007 , pp. 541 -- 546 . C. Lin and H. Zhou, \"Clock skew scheduling with delay padding for prescribed skew domains,\" in Proc. Asia South Pacific Design Automation Conf., Jan. 2007, pp. 541--546."},{"key":"e_1_3_2_1_21_1","first-page":"156","volume-title":"Int. Conf. on Computer-Aided Design","author":"Shenoy N.","year":"1993","unstructured":"N. Shenoy , R. Brayton , and A. Sangiovanni-Vincentelli , \" Minimum padding to satisfy short path constraints,\" in Proc . Int. Conf. on Computer-Aided Design , Nov. 1993 , pp. 156 -- 161 . N. Shenoy, R. Brayton, and A. Sangiovanni-Vincentelli, \"Minimum padding to satisfy short path constraints,\" in Proc. Int. Conf. on Computer-Aided Design, Nov. 1993, pp. 156--161."},{"key":"e_1_3_2_1_22_1","unstructured":"http:\/\/www.opencores.org\/.  http:\/\/www.opencores.org\/."},{"key":"e_1_3_2_1_23_1","volume-title":"Tech. Rep. UCB\/ERL M92\/41.","author":"Sentovich E.","year":"1992","unstructured":"E. Sentovich May 1992 , Tech. Rep. UCB\/ERL M92\/41. E. Sentovich et al. May 1992, Tech. Rep. UCB\/ERL M92\/41."}],"event":{"name":"ICCAD '09: The International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE Council on Electronic Design Automation (CEDA)"],"location":"San Jose California","acronym":"ICCAD '09"},"container-title":["Proceedings of the 2009 International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1687399.1687471","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1687399.1687471","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:26:22Z","timestamp":1750278382000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1687399.1687471"}},"subtitle":["optimizing high-performance pulsed-latch-based circuits"],"short-title":[],"issued":{"date-parts":[[2009,11,2]]},"references-count":23,"alternative-id":["10.1145\/1687399.1687471","10.1145\/1687399"],"URL":"https:\/\/doi.org\/10.1145\/1687399.1687471","relation":{},"subject":[],"published":{"date-parts":[[2009,11,2]]},"assertion":[{"value":"2009-11-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}