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This benchmark suite includes seven designs; one design targets fine-grained FPGA fabrics allowing for quick state-of-the-art evaluation, and six designs are specified at a high level allowing them to target a range of existing and future reconfigurable technologies. Each of the six designs can be stimulated with the help of synthetically generated input stimuli created by an open-source tool included in the downloadable suite. Another tool is included to help verify the correctness of each implemented design. To demonstrate the potential of this benchmark suite, we evaluate the power consumption of two modern industrial FPGAs targeting the mobile domain. Also, we show how an academic FPGA framework, VPR 5.0, that has been updated for power estimates can be used to estimates the power consumption of different FPGA architectures and an open-source CAD flow mapping to these architectures.<\/jats:p>","DOI":"10.1145\/1698759.1698764","type":"journal-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T19:20:32Z","timestamp":1267557632000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Benchmarking and evaluating reconfigurable architectures targeting the mobile domain"],"prefix":"10.1145","volume":"15","author":[{"given":"Peter","family":"Jamieson","sequence":"first","affiliation":[{"name":"Miami University, Oxford, OH"}]},{"given":"Tobias","family":"Becker","sequence":"additional","affiliation":[{"name":"Imperial College, London, UK"}]},{"given":"Peter Y. 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