{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:13Z","timestamp":1750308793016,"version":"3.41.0"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2010,2]]},"abstract":"<jats:p>\n            Maximum operating frequency (\n            <jats:italic>F<\/jats:italic>\n            <jats:sub>\n              <jats:italic>max<\/jats:italic>\n            <\/jats:sub>\n            ) of a system often needs to be determined at multiple operating points, defined by voltage and temperatures. Such calibration is important for the speed binning process, where the voltage-frequency (V-\n            <jats:italic>F<\/jats:italic>\n            <jats:sub>\n              <jats:italic>max<\/jats:italic>\n            <\/jats:sub>\n            ) relation needs to be accurately determined to sort chips into different bins that can be used for different applications. Moreover, adaptive systems typically require\n            <jats:italic>F<\/jats:italic>\n            <jats:sub>\n              <jats:italic>max<\/jats:italic>\n            <\/jats:sub>\n            calibration at multiple operating points in order to dynamically change operating condition such as supply voltage or body bias for power, temperature, or throughput management. For example, a Dynamic Voltage and Frequency Scaling (DVFS) system requires accurate delay calibration at multiple operating voltages in order to apply the correct operating frequency corresponding to a scaled supply. In this article, we propose a low-overhead design technique that allows efficient characterization of\n            <jats:italic>F<\/jats:italic>\n            <jats:sub>\n              <jats:italic>max<\/jats:italic>\n            <\/jats:sub>\n            at different operating voltages and temperatures. The proposed method selects a set of representative timing paths in a circuit based on their temperature and voltage sensitivities and dynamically configures them into a ring oscillator to compute the critical path delay. Compared to existing\n            <jats:italic>F<\/jats:italic>\n            <jats:sub>\n              <jats:italic>max<\/jats:italic>\n            <\/jats:sub>\n            calibration approaches, the proposed approach provides the following two main advantages: (1) it introduces a delay sensitivity metric to isolate few representative timing paths; (2) it considers actual timing paths instead of critical path replicas, thereby accounting for local within-die delay variations. The all-digital calibration method is robust under process variations and achieves high delay estimation accuracy (&gt; 4% error) at the cost of negligible design overhead (1.7% in delay, 0.3% in power, and 3.5% in die-area).\n          <\/jats:p>","DOI":"10.1145\/1698759.1698769","type":"journal-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T19:20:32Z","timestamp":1267557632000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Low-overhead\n            <i>F<\/i>\n            <sub>\n              <i>max<\/i>\n            <\/sub>\n            calibration at multiple operating points using delay-sensitivity-based path selection"],"prefix":"10.1145","volume":"15","author":[{"given":"Somnath","family":"Paul","sequence":"first","affiliation":[{"name":"Case Western Reserve University, Cleveland, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Mahmoodi","sequence":"additional","affiliation":[{"name":"San Francisco State University, San Francisco, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[{"name":"Case Western Reserve University, Cleveland, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,3,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065717"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"e_1_2_1_3_1","unstructured":"Bushnell M. L. and Agrawal V. D. 2000. Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Springer.  Bushnell M. L. and Agrawal V. D. 2000. Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Springer."},{"volume-title":"Proceedings of the International Test Conference.","author":"Chan A.","key":"e_1_2_1_4_1","unstructured":"Chan , A. and Roberts , G . 2001. A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line . In Proceedings of the International Test Conference. Chan, A. and Roberts, G. 2001. A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. In Proceedings of the International Test Conference."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232255"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe Conference.","author":"Daga J. M.","key":"e_1_2_1_6_1","unstructured":"Daga , J. M. and Auvergne , D . 1998. Temperature effect on delay for low voltage application . In Proceedings of the Design, Automation and Test in Europe Conference. Daga, J. M. and Auvergne, D. 1998. Temperature effect on delay for low voltage application. In Proceedings of the Design, Automation and Test in Europe Conference."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233628"},{"volume-title":"Proceedings of the IEEE Conference on Custom Integrated Circuits. 441--444","author":"Ha P.","key":"e_1_2_1_8_1","unstructured":"Ha , P. , Mule , T. , and Meindl , J. D . 1999. Characterization and modeling of clock skew with process variations . In Proceedings of the IEEE Conference on Custom Integrated Circuits. 441--444 . Ha, P., Mule, T., and Meindl, J. D. 1999. Characterization and modeling of clock skew with process variations. In Proceedings of the IEEE Conference on Custom Integrated Circuits. 441--444."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e90-a.4.741"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/648020.745636"},{"volume-title":"Proceedings of the International Solid-State Circuits Conference.","author":"Karl E.","key":"e_1_2_1_11_1","unstructured":"Karl , E. et al. 2008. Compact in-situ sensors for monitoring negative-bias-temperature-instability effect and oxide degradation . In Proceedings of the International Solid-State Circuits Conference. Karl, E. et al. 2008. Compact in-situ sensors for monitoring negative-bias-temperature-instability effect and oxide degradation. In Proceedings of the International Solid-State Circuits Conference."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283821"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884860"},{"volume-title":"Proceedings of the IEEE International Symposium on Semiconductor Manufacturing.","author":"Lee J.","key":"e_1_2_1_14_1","unstructured":"Lee , J. , Walker , D. M. H. , Milor , L. , Peng , Y. , and Hill , G . 1999. IC performance prediction for test cost-reduction . In Proceedings of the IEEE International Symposium on Semiconductor Manufacturing. Lee, J., Walker, D. M. H., Milor, L., Peng, Y., and Hill, G. 1999. IC performance prediction for test cost-reduction. In Proceedings of the IEEE International Symposium on Semiconductor Manufacturing."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859902"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.40"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232253"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343841"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065780"},{"volume-title":"Proceedings of the International Test Conference. 31--37","author":"Zeng J.","key":"e_1_2_1_22_1","unstructured":"Zeng , J. , Abadir , M. , Kolhatkar , A. , Vandling , G. , Wang , L. , and Abraham , J . 2004. On correlating structural tests with functional tests for speed binning of high performance design . In Proceedings of the International Test Conference. 31--37 . Zeng, J., Abadir, M., Kolhatkar, A., Vandling, G., Wang, L., and Abraham, J. 2004. On correlating structural tests with functional tests for speed binning of high performance design. In Proceedings of the International Test Conference. 31--37."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1698759.1698769","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1698759.1698769","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:58Z","timestamp":1750278178000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1698759.1698769"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":22,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2010,2]]}},"alternative-id":["10.1145\/1698759.1698769"],"URL":"https:\/\/doi.org\/10.1145\/1698759.1698769","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2010,2]]},"assertion":[{"value":"2009-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-03-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}