{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:12Z","timestamp":1750308792745,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2010,2]]},"abstract":"<jats:p>We propose a technique that leverages configurable data caches to address the problem of energy inefficiency and intertask interference in multitasking embedded systems. Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Caches contribute to a significant amount of power as they typically occupy a large part of the chip and are accessed frequently. In nanometer technologies, such large structures contribute significantly to the total leakage power as well. Additionally, cache outcomes in multitasking environments are notoriously difficult to predict, if not impossible, thus resulting in poor real-time guarantees. We study the effect of multiprogramming workloads on the data cache in a preemptive multitasking environment, and propose a technique which leverages configurable cache architectures to not only eliminate intertask cache interference, but also to significantly reduce both dynamic and leakage power. By mapping tasks to different cache partitions, interference is completely eliminated. Dynamic and leakage power are significantly reduced as only a subset of the cache is active at any moment. We introduce a profile-based, off-line algorithm, which identifies a beneficial cache partitioning. The OS configures the data cache during context-switch by activating the corresponding partition. Our experiments on a large set of multitasking benchmarks demonstrate that our technique not only efficiently eliminates intertask interference, but also significantly reduces both dynamic and leakage power.<\/jats:p>","DOI":"10.1145\/1698772.1698774","type":"journal-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T19:20:32Z","timestamp":1267557632000},"page":"1-35","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["Cache partitioning for energy-efficient and interference-free embedded multitasking"],"prefix":"10.1145","volume":"9","author":[{"given":"Rakesh","family":"Reddy","sequence":"first","affiliation":[{"name":"InHand Electronics, Inc., Rockwille, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Petrov","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,3,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/48012.48037"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320119"},{"volume-title":"Proceedings of the Static Analysis Symposium (SAS'96)","author":"Alt M.","key":"e_1_2_1_3_1","unstructured":"Alt , M. , Ferdinand , C. , Martin , F. , and Wilhelm , R . 1996. Cache behaviour prediction by abstract interpretation . In Proceedings of the Static Analysis Symposium (SAS'96) . Springer, Berlin, 52--66. Alt, M., Ferdinand, C., Martin, F., and Wilhelm, R. 1996. Cache behaviour prediction by abstract interpretation. In Proceedings of the Static Analysis Symposium (SAS'96). Springer, Berlin, 52--66."},{"volume-title":"ARM920T Technical Reference Manual","author":"Ltd","key":"e_1_2_1_4_1","unstructured":"ARM Ltd . ARM920T Technical Reference Manual . ARM Ltd . ARM Ltd. ARM920T Technical Reference Manual. ARM Ltd."},{"volume-title":"Proceedings of the Real-Time Systems Symposium (RTSS'94)","author":"Arnold R.","key":"e_1_2_1_5_1","unstructured":"Arnold , R. , Mueller , F. , Whalley , D. , and Harmon , M . 1994. Bounding worst-case instruction cache performance . In Proceedings of the Real-Time Systems Symposium (RTSS'94) . IEEE, Los Alamitos, CA, 172--181. Arnold, R., Mueller, F., Whalley, D., and Harmon, M. 1994. Bounding worst-case instruction cache performance. In Proceedings of the Real-Time Systems Symposium (RTSS'94). IEEE, Los Alamitos, CA, 172--181."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.621215"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"volume-title":"Proceedings of the IEEE Conference on Communications, Computers and Signal Processing (PACRIM). IEEE","author":"Chen H.-C.","key":"e_1_2_1_9_1","unstructured":"Chen , H.-C. and Chiang , J . -S. 2001. A highly configurable cache architecture for embedded systems . In Proceedings of the IEEE Conference on Communications, Computers and Signal Processing (PACRIM). IEEE , Los Alamitos, CA, 315--318. Chen, H.-C. and Chiang, J.-S. 2001. A highly configurable cache architecture for embedded systems. In Proceedings of the IEEE Conference on Communications, Computers and Signal Processing (PACRIM). IEEE, Los Alamitos, CA, 315--318."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337523"},{"volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA'02)","author":"Flautner K.","key":"e_1_2_1_11_1","unstructured":"Flautner , K. , Kim , N. , Martin , S. , Blaauw , D. , and Mudge , T . 2002. Drowsy caches: Simple techniques for reducing leakage power . In Proceedings of the International Symposium on Computer Architecture (ISCA'02) . ACM, New York, 148--157. Flautner, K., Kim, N., Martin, S., Blaauw, D., and Mudge, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of the International Symposium on Computer Architecture (ISCA'02). ACM, New York, 148--157."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278537"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.814618"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1113830.1113836"},{"volume-title":"Intel XScale Microarchitecture","author":"Intel Corporation","key":"e_1_2_1_15_1","unstructured":"Intel Corporation . Intel XScale Microarchitecture . Intel Corporation . Intel Corporation. Intel XScale Microarchitecture. Intel Corporation."},{"volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO'02)","author":"Kim N.","key":"e_1_2_1_16_1","unstructured":"Kim , N. , Flautner , K. , Blaauw , D. , and Mudge , T . 2002. Drowsy instruction caches, leakage power reduction using dynamic voltage scaling and cache sub-bank prediction . In Proceedings of the International Symposium on Microarchitecture (MICRO'02) . IEEE, Los Alamitos, CA, 219--230. Kim, N., Flautner, K., Blaauw, D., and Mudge, T. 2002. Drowsy instruction caches, leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. In Proceedings of the International Symposium on Microarchitecture (MICRO'02). IEEE, Los Alamitos, CA, 219--230."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013254"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1989.63574"},{"volume-title":"Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS'01)","author":"Kirner R.","key":"e_1_2_1_19_1","unstructured":"Kirner , R. and Puschner , P . 2001. Transformation of path information for wcet analysis during compilation . In Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS'01) . IEEE, Los Alamitos, CA, 29. Kirner, R. and Puschner, P. 2001. Transformation of path information for wcet analysis during compilation. In Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS'01). IEEE, Los Alamitos, CA, 29."},{"volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO'97)","author":"Lee C.","key":"e_1_2_1_20_1","unstructured":"Lee , C. , Potkonjak , M. , and Mangione-Smith , W. H . 1997. Media bench: A tool for evaluating and synthesizing multimedia and communications systems . In Proceedings of the International Symposium on Microarchitecture (MICRO'97) . IEEE, Los Alamitos, CA, 330--335. Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. Media bench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture (MICRO'97). IEEE, Los Alamitos, CA, 330--335."},{"volume-title":"Proceedings of the IEEE Real-Time Systems Symposium. IEEE","author":"Li Y. S.","key":"e_1_2_1_21_1","unstructured":"Li , Y. S. , Malik , S. , and Wolfe , A . 1997. Cache modeling for real-time software . In Proceedings of the IEEE Real-Time Systems Symposium. IEEE , Los Alamitos, CA, 148--157. Li, Y. S., Malik, S., and Wolfe, A. 1997. Cache modeling for real-time software. In Proceedings of the IEEE Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 148--157."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344610"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106982"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/216636.216677"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344526"},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). IEEE","author":"Powell M.","key":"e_1_2_1_26_1","unstructured":"Powell , M. , Yang , S.-H. , Falsafi , B. , Roy , K. , and Vijaykumar , T. N . 2001. An integrated circuit\/architecture approach to reducing leakage in deep-submicron high-performance i-caches . In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). IEEE , Los Alamitos, CA, 147--157. Powell, M., Yang, S.-H., Falsafi, B., Roy, K., and Vijaykumar, T. N. 2001. An integrated circuit\/architecture approach to reducing leakage in deep-submicron high-performance i-caches. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). IEEE, Los Alamitos, CA, 147--157."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/997163.997184"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2006.33"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1274858.1274863"},{"volume-title":"Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02)","author":"Suh G.","key":"e_1_2_1_32_1","unstructured":"Suh , G. , Devadas , S. , and Rudolph , L . 2002. A new memory monitoring scheme for memory - aware scheduling and partitioning . In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02) . IEEE, Los Alamitos, CA, 117--128. Suh, G., Devadas, S., and Rudolph, L. 2002. A new memory monitoring scheme for memory - aware scheduling and partitioning. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02). IEEE, Los Alamitos, CA, 117--128."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065910.1065935"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/IWIA.2003.1262779"},{"key":"e_1_2_1_35_1","unstructured":"Thoziyoor S. Muralimanohar N. Ahn J. and Jouppi N. 2008. Cacti 5.1. Tech. rep. HP Laboratories Palo Alto. April.  Thoziyoor S. Muralimanohar N. Ahn J. and Jouppi N. 2008. Cacti 5.1. Tech. rep. HP Laboratories Palo Alto. April."},{"volume-title":"Proceedings of the Real-Time Systems Symposium. IEEE","author":"Vera X.","key":"e_1_2_1_36_1","unstructured":"Vera , X. , Lisper , B. , and Jingling , X . 2003. Data caches in multitasking hard real-time systems . In Proceedings of the Real-Time Systems Symposium. IEEE , Los Alamitos, CA, 145--165. Vera, X., Lisper, B., and Jingling, X. 2003. Data caches in multitasking hard real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 145--165."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165606"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/200781.200792"},{"volume-title":"Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02)","author":"Yang S.-H.","key":"e_1_2_1_39_1","unstructured":"Yang , S.-H. , Falsafi , B. , Powell , M. D. , and Vijaykumar , T. N . 2002. Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay . In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02) . IEEE, Los Alamitos, CA, 151. Yang, S.-H., Falsafi, B., Powell, M. D., and Vijaykumar, T. N. 2002. Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02). IEEE, Los Alamitos, CA, 151."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993405"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1698772.1698774","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1698772.1698774","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:58Z","timestamp":1750278178000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1698772.1698774"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":41,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2010,2]]}},"alternative-id":["10.1145\/1698772.1698774"],"URL":"https:\/\/doi.org\/10.1145\/1698772.1698774","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2010,2]]},"assertion":[{"value":"2008-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-03-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}