{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:06:49Z","timestamp":1759147609943,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,3,14]],"date-time":"2010-03-14T00:00:00Z","timestamp":1268524800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,3,14]]},"DOI":"10.1145\/1735023.1735064","type":"proceedings-article","created":{"date-parts":[[2010,3,16]],"date-time":"2010-03-16T19:27:05Z","timestamp":1268767625000},"page":"177-184","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles"],"prefix":"10.1145","author":[{"given":"Iris H.-R.","family":"Jiang","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan Roc"}]},{"given":"Hua-Yu","family":"Chang","sequence":"additional","affiliation":[{"name":"Freelance, Taipei, Taiwan Roc"}]},{"given":"Chih-Long","family":"Chang","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan Roc"}]}],"member":"320","published-online":{"date-parts":[[2010,3,14]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ITRS. http:\/\/www.itrs.net.  ITRS. http:\/\/www.itrs.net."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1969.16754"},{"key":"e_1_3_2_1_3_1","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"Weste N. E.","year":"2005","unstructured":"N. E. Weste and D. M. Harris . CMOS VLSI Design: A Circuits and Systems Perspective , 3 rd ed., Addison Wesley , 2005 . N. E. Weste and D. M. Harris. CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed., Addison Wesley, 2005.","edition":"3"},{"key":"e_1_3_2_1_4_1","unstructured":"Cadence Virtuoso. http:\/\/www.cadence.com.  Cadence Virtuoso. http:\/\/www.cadence.com."},{"key":"e_1_3_2_1_5_1","unstructured":"Synopsys PrimeRail. http:\/\/www.synopsys.com.  Synopsys PrimeRail. http:\/\/www.synopsys.com."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.256927"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343817"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337505"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119946"},{"key":"e_1_3_2_1_10_1","first-page":"1692","volume-title":"Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS-08)","author":"Yan J.-T.","year":"2008","unstructured":"J.-T. Yan , and Z.-W. Chen . Electromigration-aware rectilinear Steiner tree construction for analog circuits . In Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS-08) , pages 1692 -- 1695 , 2008 . J.-T. Yan, and Z.-W. Chen. Electromigration-aware rectilinear Steiner tree construction for analog circuits. In Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS-08), pages 1692--1695, 2008."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123017"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1370949"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1137\/0132071"},{"key":"e_1_3_2_1_14_1","volume-title":"Introduction to Algorithms","author":"Cormen T. H.","year":"2001","unstructured":"T. H. Cormen , C. E. Leiserson , R. E. Rivest , and C. Stein . Introduction to Algorithms , 2 nd ed., MIT Press , 2001 . T. H. Cormen, C. E. Leiserson, R. E. Rivest, and C. Stein. Introduction to Algorithms, 2nd ed., MIT Press, 2001.","edition":"2"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/76359.76368"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917583"},{"key":"e_1_3_2_1_17_1","unstructured":"The LEDA package. http:\/\/www.algorithmic-solutions.com.  The LEDA package. http:\/\/www.algorithmic-solutions.com."}],"event":{"name":"ISPD '10: International Symposium on Physical Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS"],"location":"San Francisco California USA","acronym":"ISPD '10"},"container-title":["Proceedings of the 19th international symposium on Physical design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1735023.1735064","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1735023.1735064","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:29:43Z","timestamp":1750285783000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1735023.1735064"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3,14]]},"references-count":17,"alternative-id":["10.1145\/1735023.1735064","10.1145\/1735023"],"URL":"https:\/\/doi.org\/10.1145\/1735023.1735064","relation":{},"subject":[],"published":{"date-parts":[[2010,3,14]]},"assertion":[{"value":"2010-03-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}