{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,21]],"date-time":"2026-09-21T10:16:14Z","timestamp":1789985774346,"version":"4.0.1"},"publisher-location":"New York, NY, USA","reference-count":32,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,3,13]],"date-time":"2010-03-13T00:00:00Z","timestamp":1268438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,3,13]]},"DOI":"10.1145\/1736020.1736058","type":"proceedings-article","created":{"date-parts":[[2010,3,16]],"date-time":"2010-03-16T15:27:05Z","timestamp":1268753225000},"page":"335-346","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":184,"title":["Fairness via source throttling"],"prefix":"10.1145","author":[{"given":"Eiman","family":"Ebrahimi","sequence":"first","affiliation":[{"name":"The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chang Joo","family":"Lee","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University , Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yale N.","family":"Patt","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2010,3,13]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Advanced Micro Devices. AMD's six-core Opteron processors. http:\/\/techreport.com\/articles.x\/17005 2009.  Advanced Micro Devices. AMD's six-core Opteron processors. http:\/\/techreport.com\/articles.x\/17005 2009."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771801"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.37"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669150"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508260"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299108"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.25"},{"key":"e_1_3_2_1_8_1","volume-title":"ASPLOS Wild and Crazy Idea Session '98","author":"Glew A.","year":"1998","unstructured":"A. Glew . MLP yes! ILP no! In ASPLOS Wild and Crazy Idea Session '98 , Oct. 1998 . A. Glew. MLP yes! ILP no! In ASPLOS Wild and Crazy Idea Session '98, Oct. 1998."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669149"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542342"},{"key":"e_1_3_2_1_11_1","volume-title":"Intel Technical White Paper","year":"2008","unstructured":"Intel. First the tick, now the tock: Next generation Intel microarchitecure (Nehalem) . Intel Technical White Paper , 2008 . Intel. First the tick, now the tock: Next generation Intel microarchitecure (Nehalem). Intel Technical White Paper, 2008."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531743.1531747"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1026001"},{"key":"e_1_3_2_1_16_1","volume-title":"ISCA-8","author":"Kroft D.","year":"1981","unstructured":"D. Kroft . Lockup-free instruction fetch\/prefetch cache organization. In ISCA-8 , 1981 . D. Kroft. Lockup-free instruction fetch\/prefetch cache organization. In ISCA-8, 1981."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.31"},{"key":"e_1_3_2_1_18_1","volume-title":"ISPASS","author":"Luo K.","year":"2001","unstructured":"K. Luo Balancing throughput and fairness in SMT processors . In ISPASS , 2001 . K. Luo et al. Balancing throughput and fairness in SMT processors. In ISPASS, 2001."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/645609.662954"},{"key":"e_1_3_2_1_20_1","unstructured":"Micron. Datasheet: 2Gb DDR3 SDRAM MT41J512M4 -- 64 Meg x 4 x 8 banks http:\/\/download.micron.com\/pdf\/datasheets\/dram\/ddr3.  Micron. Datasheet: 2Gb DDR3 SDRAM MT41J512M4 -- 64 Meg x 4 x 8 banks http:\/\/download.micron.com\/pdf\/datasheets\/dram\/ddr3."},{"key":"e_1_3_2_1_21_1","volume-title":"USENIX Security","author":"Moscibroda T.","year":"2007","unstructured":"T. Moscibroda and O. Mutlu . Memory performance attacks: Denial of memory service in multi--core systems . In USENIX Security , 2007 . T. Moscibroda and O. Mutlu. Memory performance attacks: Denial of memory service in multi--core systems. In USENIX Security, 2007."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250671"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.28"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"e_1_3_2_1_29_1","volume-title":"Oct.","author":"Tendler J.","year":"2001","unstructured":"J. Tendler POWER4 system microarchitecture. IBM Technical White Paper , Oct. 2001 . J. Tendler et al. POWER4 system microarchitecture. IBM Technical White Paper, Oct. 2001."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"e_1_3_2_1_31_1","volume-title":"Intel Technical White Paper","author":"Wechsler O.","year":"2006","unstructured":"O. Wechsler . Inside Intel core microarchitecure . Intel Technical White Paper , 2006 . O. Wechsler. Inside Intel core microarchitecure. Intel Technical White Paper, 2006."},{"key":"e_1_3_2_1_32_1","volume-title":"USENIX","author":"Zhang X.","year":"2009","unstructured":"X. Zhang Hardware execution throttling for multi-core resource management . In USENIX , 2009 . X. Zhang et al. Hardware execution throttling for multi-core resource management. In USENIX, 2009."}],"event":{"name":"ASPLOS '10: Architectural Support for Programming Languages and Operating Systems","location":"Pittsburgh Pennsylvania USA","acronym":"ASPLOS '10","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1736020.1736058","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1736020.1736058","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:41:22Z","timestamp":1750236082000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1736020.1736058"}},"subtitle":["a configurable and high-performance fairness substrate for multi-core memory systems"],"short-title":[],"issued":{"date-parts":[[2010,3,13]]},"references-count":32,"alternative-id":["10.1145\/1736020.1736058","10.1145\/1736020"],"URL":"https:\/\/doi.org\/10.1145\/1736020.1736058","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1735970.1736058","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1735971.1736058","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2010,3,13]]},"assertion":[{"value":"2010-03-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}