{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:03Z","timestamp":1750308783008,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,2,26]],"date-time":"2010-02-26T00:00:00Z","timestamp":1267142400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,2,26]]},"DOI":"10.1145\/1741906.1741918","type":"proceedings-article","created":{"date-parts":[[2010,3,30]],"date-time":"2010-03-30T12:32:28Z","timestamp":1269952348000},"page":"64-69","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Dynamic cluster resource allocations for jobs with known memory demands"],"prefix":"10.1145","author":[{"given":"D. A.","family":"Vidhate","sequence":"first","affiliation":[{"name":"College of Engineering, Ahmednagar, India"}]},{"given":"A. K.","family":"Patil","sequence":"additional","affiliation":[{"name":"College of Engineering, Ahmednagar, India"}]},{"given":"D. V.","family":"Guleria","sequence":"additional","affiliation":[{"name":"College of Engineering, Ahmednagar, India"}]}],"member":"320","published-online":{"date-parts":[[2010,2,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/301453.301478"},{"issue":"3","key":"e_1_3_2_1_2_1","first-page":"4","article-title":"Memory ushering in a Scalable Computing Cluster","volume":"22","author":"Barak A.","year":"1998","unstructured":"A. Barak & A. Braverman , \" Memory ushering in a Scalable Computing Cluster \", J. Microprocessors & Microsystems , vol. 22 , no. 3 -- 4 , pp. 175--182, Aug. 1998 . A. Barak & A. Braverman, \"Memory ushering in a Scalable Computing Cluster\", J. Microprocessors & Microsystems, vol. 22, no. 3--4, pp. 175--182, Aug. 1998.","journal-title":"J. Microprocessors & Microsystems"},{"key":"e_1_3_2_1_3_1","first-page":"109","volume-title":"Proc. 14th Int'l Parallel & Distributed Processing Symp.","author":"Batat A.","year":"2000","unstructured":"A. Batat & D. G. Feitelson , \" Gang Scheduling with Memory Considerations\" , Proc. 14th Int'l Parallel & Distributed Processing Symp. , pp. 109 -- 114 , May 2000 . A. Batat & D. G. Feitelson, \"Gang Scheduling with Memory Considerations\", Proc. 14th Int'l Parallel & Distributed Processing Symp., pp. 109--114, May 2000."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4434.788780"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/646376.689370"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/55595.55604"},{"key":"e_1_3_2_1_7_1","volume-title":"http:\/\/www.cs.huji.ac.il\/labs\/parallel\/workload\/logs.html\\#anlcm5","author":"Feitelson D.","year":"1998","unstructured":"D. Feitelson , \" The Parallel Workload Archive\" , http:\/\/www.cs.huji.ac.il\/labs\/parallel\/workload\/logs.html\\#anlcm5 , 1998 . D. Feitelson, \"The Parallel Workload Archive\", http:\/\/www.cs.huji.ac.il\/labs\/parallel\/workload\/logs.html\\#anlcm5, 1998."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380210802"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/258612.258681"},{"key":"e_1_3_2_1_10_1","volume-title":"Patterson Computer Architecture: A Quantitative Approach","author":"Hennessy J. L.","year":"1996","unstructured":"J. L. Hennessy & D. A. Patterson Computer Architecture: A Quantitative Approach , second ed, Morgan Kaufmann , 1996 . J. L. Hennessy & D. A. Patterson Computer Architecture: A Quantitative Approach, second ed, Morgan Kaufmann, 1996."},{"key":"e_1_3_2_1_11_1","first-page":"383","volume-title":"ed","author":"Flouris M. D.","year":"1999","unstructured":"M. D. Flouris & E. P. Markatos , \" Network RAM , \" High Performance Cluster Computing , Chapter 16, R. Buyya , ed , vol. 1 , pp. 383 -- 508 , new Jersey : Prentice Hall 1999 . M. D. Flouris & E. P. Markatos, \"Network RAM, \"High Performance Cluster Computing, Chapter 16, R. Buyya, ed, vol. 1, pp. 383--508, new Jersey: Prentice Hall 1999."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/263326.263344"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/224056.224072"},{"key":"e_1_3_2_1_14_1","first-page":"95","volume-title":"Rendering '97 sump","author":"Ma K. L.","year":"1997","unstructured":"K. L. Ma & T. W. Ctockett , \" A Scalable , cell-projection volume Rendering '97 sump , pp. 95 -- 104 , oct. 1997 . K. L. Ma & T. W. Ctockett, \"A Scalable, cell-projection volume Rendering '97 sump, pp. 95--104, oct. 1997."},{"key":"e_1_3_2_1_15_1","first-page":"109","volume-title":"Conf. Distributed Computing Systems","author":"Chen S.","year":"2001","unstructured":"S. Chen , L. Xiao , & X. Zhang , \" Dynamic Load Sharing with Unknown memory Demands of Jobs in Clusters ,\"proc. 21st Int'l Conf. Distributed Computing Systems , pp. 109 -- 118 , Apr. 2001 . S. Chen, L. Xiao, & X. Zhang, \"Dynamic Load Sharing with Unknown memory Demands of Jobs in Clusters,\"proc. 21st Int'l Conf. Distributed Computing Systems, pp. 109--118, Apr. 2001."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.83908"},{"key":"e_1_3_2_1_17_1","first-page":"301","volume-title":"High-performance Computer Architecture","author":"Lin W.","year":"2001","unstructured":"W. Lin , S. K. Reinhardt , & D. Burger , \" Reducing DRAM Latencies with an Integrated Memory Hierarchy Design, \"Proc. Seventh Int'l symp . High-performance Computer Architecture , pp. 301 -- 312 , jan. 2001 . W. Lin, S. K. Reinhardt, & D. Burger, \"Reducing DRAM Latencies with an Integrated Memory Hierarchy Design, \"Proc. Seventh Int'l symp. High-performance Computer Architecture, pp. 301--312, jan. 2001."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1997.1378"}],"event":{"name":"ICWET '10: International Conference and Workshop on Emerging Trends in Technology","sponsor":["UNITECH Unitech Engineers, India","AICTE All India Council for Technical Education","SIGAI ACM Special Interest Group on Artificial Intelligence","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Mumbai Maharashtra India","acronym":"ICWET '10"},"container-title":["Proceedings of the International Conference and Workshop on Emerging Trends in Technology"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1741906.1741918","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1741906.1741918","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:44Z","timestamp":1750278164000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1741906.1741918"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2,26]]},"references-count":18,"alternative-id":["10.1145\/1741906.1741918","10.1145\/1741906"],"URL":"https:\/\/doi.org\/10.1145\/1741906.1741918","relation":{},"subject":[],"published":{"date-parts":[[2010,2,26]]},"assertion":[{"value":"2010-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}