{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:59:26Z","timestamp":1761580766899,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,2,26]],"date-time":"2010-02-26T00:00:00Z","timestamp":1267142400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,2,26]]},"DOI":"10.1145\/1741906.1742098","type":"proceedings-article","created":{"date-parts":[[2010,3,30]],"date-time":"2010-03-30T12:32:28Z","timestamp":1269952348000},"page":"828-833","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings"],"prefix":"10.1145","author":[{"given":"B.","family":"Sen","sequence":"first","affiliation":[{"name":"National Institute of Technology, Durgapur, WB, India"}]},{"given":"M.","family":"Dalui","sequence":"additional","affiliation":[{"name":"Haldia Institute of Technology, Haldia, WB, India"}]},{"given":"B. K.","family":"Sikdar","sequence":"additional","affiliation":[{"name":"Bengal Engineering and Science University, Howrah, WB, India"}]}],"member":"320","published-online":{"date-parts":[[2010,2,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.277.5328.928"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.124043"},{"key":"e_1_3_2_1_3_1","first-page":"433","volume-title":"Proceedings of 11th IEEE VLSI Design and Test Symposium","author":"Sen B.","year":"2007","unstructured":"B. Sen and B. K. Sikdar , ' Characterization of universal Nand-Nor-Inverter QCA gate ', in Proceedings of 11th IEEE VLSI Design and Test Symposium , Kolkata , pp. 433 -- 442 , Aug 2007 ,. B. Sen and B. K. Sikdar, 'Characterization of universal Nand-Nor-Inverter QCA gate', in Proceedings of 11th IEEE VLSI Design and Test Symposium, Kolkata, pp. 433--442, Aug 2007,."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/4\/1\/004"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1021\/ja026856g"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/795678.797347"},{"key":"e_1_3_2_1_7_1","first-page":"710","volume-title":"IEEE TCAD","volume":"12","author":"Dietmeyer D. L.","year":"1993","unstructured":"D. L. Dietmeyer , 'Generating minimal covers of symmetric function ', IEEE TCAD , Vol. 12 , no. 5, pp. 710 -- 713 , May 1993 . D. L. Dietmeyer, 'Generating minimal covers of symmetric function', IEEE TCAD, Vol. 12, no. 5, pp. 710--713, May 1993."},{"key":"e_1_3_2_1_8_1","first-page":"284","volume-title":"Proceedings, Asian Test Symposium (ATS), IEEE CS Press, USA","author":"Rahman H.","year":"2003","unstructured":"H. Rahman . D. K. Das and B. B. Bhattacharya , Mapping symmetric functions to hierarchical modules for path-delay fault testability ', Proceedings, Asian Test Symposium (ATS), IEEE CS Press, USA , pp. 284 -- 289 , Nov. 2003 . H. Rahman. D. K. Das and B. B. Bhattacharya, Mapping symmetric functions to hierarchical modules for path-delay fault testability', Proceedings, Asian Test Symposium (ATS), IEEE CS Press, USA, pp. 284--289, Nov. 2003."},{"key":"e_1_3_2_1_9_1","volume-title":"IEEE DTIS","author":"Rahman H.","year":"2006","unstructured":"H. Rahman , B. K. Sikdar and D. K. Das , ' Synthesis of Symmetric Functions Using Quantum Cellular Automata ', IEEE DTIS , Tunis, Tunisia , Sept 2006 . H. Rahman, B. K. Sikdar and D. K. Das, 'Synthesis of Symmetric Functions Using Quantum Cellular Automata', IEEE DTIS, Tunis, Tunisia, Sept 2006."},{"key":"e_1_3_2_1_10_1","volume-title":"IEEE conference on nanotechnology","author":"Huang J.","year":"2005","unstructured":"J. Huang , M. Momenzadeh , L. Schiano anf F. Lombardi . 'Simulation-based design of modular QCA circuits ', IEEE conference on nanotechnology , Nagoya , 2005 . J. Huang, M. Momenzadeh, L. Schiano anf F. Lombardi. 'Simulation-based design of modular QCA circuits', IEEE conference on nanotechnology, Nagoya, 2005."},{"key":"e_1_3_2_1_11_1","unstructured":"K. Walus et. al. 'ATIPS laboratory QCADesigner homepage' http:\/\/www.atips.ca\/projects\/qcadesigner ATIPS laboratory. Univ. of Calgary Canada 2002.  K. Walus et. al. 'ATIPS laboratory QCADesigner homepage' http:\/\/www.atips.ca\/projects\/qcadesigner ATIPS laboratory. Univ. of Calgary Canada 2002."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852667"},{"key":"e_1_3_2_1_13_1","volume-title":"VDAT","author":"Ditti S.","year":"2008","unstructured":"S. Ditti , P. K. Bhattacharya , P. Mitra and B. K. Sikdar 'Logic Realization with Coupled QCA Majority-Minority Gate ', VDAT , 2008 . S. Ditti, P. K. Bhattacharya, P. Mitra and B. K. Sikdar 'Logic Realization with Coupled QCA Majority-Minority Gate', VDAT, 2008."},{"key":"e_1_3_2_1_14_1","volume-title":"Modern digital theory","author":"Chen X. X.","year":"2001","unstructured":"X. X. Chen , X. W. Wu , ' Modern digital theory ', in Zhejiang University Press , 2001 . X. X. Chen, X. W. Wu, 'Modern digital theory', in Zhejiang University Press, 2001."},{"volume-title":"Proceedings of 11th IEEE conference on Communication Technology","year":"2008","key":"e_1_3_2_1_15_1","unstructured":"Yinshui Xia and Keming Qui 'Design and application of Univarsal logic based on Quantum-dot Cellular Automata ', in Proceedings of 11th IEEE conference on Communication Technology , 2008 . Yinshui Xia and Keming Qui 'Design and application of Univarsal logic based on Quantum-dot Cellular Automata', in Proceedings of 11th IEEE conference on Communication Technology, 2008."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF00202268"}],"event":{"name":"ICWET '10: International Conference and Workshop on Emerging Trends in Technology","sponsor":["UNITECH Unitech Engineers, India","AICTE All India Council for Technical Education","SIGAI ACM Special Interest Group on Artificial Intelligence","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Mumbai Maharashtra India","acronym":"ICWET '10"},"container-title":["Proceedings of the International Conference and Workshop on Emerging Trends in Technology"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1741906.1742098","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1741906.1742098","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:41:02Z","timestamp":1750250462000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1741906.1742098"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2,26]]},"references-count":16,"alternative-id":["10.1145\/1741906.1742098","10.1145\/1741906"],"URL":"https:\/\/doi.org\/10.1145\/1741906.1742098","relation":{},"subject":[],"published":{"date-parts":[[2010,2,26]]},"assertion":[{"value":"2010-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}