{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:32:53Z","timestamp":1750307573973,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,2,26]],"date-time":"2010-02-26T00:00:00Z","timestamp":1267142400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,2,26]]},"DOI":"10.1145\/1741906.1742115","type":"proceedings-article","created":{"date-parts":[[2010,3,30]],"date-time":"2010-03-30T12:32:28Z","timestamp":1269952348000},"page":"911-914","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Standby leakage reduction in nanoscale CMOS VLSI circuits"],"prefix":"10.1145","author":[{"given":"J.","family":"Deshmukh","sequence":"first","affiliation":[{"name":"Maulana Azad National Institute of Technology, Bhopal, India"}]},{"given":"K.","family":"Khare","sequence":"additional","affiliation":[{"name":"Maulana Azad National Institute of Technology, Bhopal, India"}]}],"member":"320","published-online":{"date-parts":[[2010,2,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.127482"},{"volume-title":"IEICE transactions on electronics","author":"Fallah Farzan","key":"e_1_3_2_1_3_1","unstructured":"Farzan Fallah and Massoud Pedram , \" Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits\" , IEICE transactions on electronics , vol. 88 , no. 4, pp. 509--519, 2005 Farzan Fallah and Massoud Pedram, \"Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits\", IEICE transactions on electronics, vol. 88, no. 4, pp. 509--519, 2005"},{"key":"e_1_3_2_1_4_1","volume-title":"IEEE Symposium on VLSI Circuits","author":"Y. Ye","year":"1998","unstructured":"Y. Ye et al. IEEE Symposium on VLSI Circuits , 1998 . Y. Ye et al. IEEE Symposium on VLSI Circuits, 1998."},{"key":"e_1_3_2_1_5_1","author":"Mukhopadhyay S.","year":"2003","unstructured":"S. Mukhopadhyay , IEEE Transactions on VLSI Systems , 2003 . S. Mukhopadhyay, IEEE Transactions on VLSI Systems, 2003.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383132"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821547"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2008.4674918"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266182"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"e_1_3_2_1_11_1","first-page":"1","article-title":"An Analysis Methodology for Dynamic Power Gating","author":"Choi Ken","year":"2007","unstructured":"Ken Choi and Jerry Frenkil , \" An Analysis Methodology for Dynamic Power Gating \", Sequence Design Inc , pp. 1 -- 13 , 26 ( July 2007 ). Ken Choi and Jerry Frenkil, \"An Analysis Methodology for Dynamic Power Gating\", Sequence Design Inc, pp. 1--13, 26 (July 2007).","journal-title":"Sequence Design Inc"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266182"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/832285.835614"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852696"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280807"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672431"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922710"},{"key":"e_1_3_2_1_18_1","first-page":"1161","volume-title":"IEEE International Symposium on Circuits and Systems, 27--30","author":"Yong-Bin Ki Kyung Ki","year":"2007","unstructured":"Kyung Ki Kim; Yong-Bin Ki , \" Optimal Body Biasing for Minimum Leakage Power in Standby Mode\" , IEEE International Symposium on Circuits and Systems, 27--30 May 2007 , Page(s): 1161 -- 1164 Kyung Ki Kim; Yong-Bin Ki, \"Optimal Body Biasing for Minimum Leakage Power in Standby Mode\", IEEE International Symposium on Circuits and Systems, 27--30 May 2007, Page(s):1161--1164"}],"event":{"name":"ICWET '10: International Conference and Workshop on Emerging Trends in Technology","sponsor":["UNITECH Unitech Engineers, India","AICTE All India Council for Technical Education","SIGAI ACM Special Interest Group on Artificial Intelligence","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Mumbai Maharashtra India","acronym":"ICWET '10"},"container-title":["Proceedings of the International Conference and Workshop on Emerging Trends in Technology"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1741906.1742115","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1741906.1742115","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:41:06Z","timestamp":1750250466000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1741906.1742115"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2,26]]},"references-count":18,"alternative-id":["10.1145\/1741906.1742115","10.1145\/1741906"],"URL":"https:\/\/doi.org\/10.1145\/1741906.1742115","relation":{},"subject":[],"published":{"date-parts":[[2010,2,26]]},"assertion":[{"value":"2010-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}