{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:04Z","timestamp":1750307404733,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2010,3,27]],"date-time":"2010-03-27T00:00:00Z","timestamp":1269648000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGMETRICS Perform. Eval. Rev."],"published-print":{"date-parts":[[2010,3,27]]},"abstract":"<jats:p>As new multi-threaded usage models such as virtualization and consolidation take advantage of multiple cores in CMP architectures, the impact of shared resource contention between VMs and user-level applications introduces Quality of Service(QoS) concerns and challenges. QoS-aware management of these shared platform resources is therefore becoming increasingly important. Various QoS schemes for resource management have been recently proposed, but most of these prior efforts have been focused on controlling individual resource allocation based on priority information passed down from the OS or Hypervisor to system resources. The complexity of this approach increases when multiple levels of resources are associated with an application's performance and power consumption. In this paper we employ simpler rate-based QoS mechanisms which control the execution rate of competing applications. To enable differentiation between simultaneously running applications' performance and power consumption, these rate mechanisms need to dynamically adjust the execution of application. Our proposed PI-RATE architecture introduces a control-theoretic approach to dynamically adjust the execution rate of each application based on the QoS target and monitored resource utilization. We evaluate three modes of PI-RATE architecture - cache QoS targets, performance QoS targets and power QoS targets - to show that the PI-RATE architecture is flexible and effective at enabling QoS in a CMP platform.<\/jats:p>","DOI":"10.1145\/1773394.1773396","type":"journal-article","created":{"date-parts":[[2010,5,6]],"date-time":"2010-05-06T17:41:18Z","timestamp":1273167678000},"page":"3-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["PIRATE"],"prefix":"10.1145","volume":"37","author":[{"given":"Ramesh","family":"Illikkal","sequence":"first","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vineet","family":"Chadha","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Herdrich","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donald","family":"Newell","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,3,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Acpi specification. http:\/\/www.acpi\/info\/spec.htm.  Acpi specification. http:\/\/www.acpi\/info\/spec.htm."},{"key":"e_1_2_1_2_1","unstructured":"Intel dual-core processors. http:\/\/www.intel.com\/technology\/computing\/dualcore\/.  Intel dual-core processors. http:\/\/www.intel.com\/technology\/computing\/dualcore\/."},{"key":"e_1_2_1_3_1","unstructured":"Pid controller. http:\/\/en.wikipedia.org\/wiki\/PID controller.  Pid controller. http:\/\/en.wikipedia.org\/wiki\/PID controller."},{"key":"e_1_2_1_4_1","unstructured":"SPEC cpu2000 benchmark. http:\/\/www.spec.org\/cpu\/.  SPEC cpu2000 benchmark. http:\/\/www.spec.org\/cpu\/."},{"key":"e_1_2_1_5_1","unstructured":"Barnes Cooper. Mobile power management. Intel Internal Presentation.  Barnes Cooper. Mobile power management. Intel Internal Presentation."},{"key":"e_1_2_1_6_1","volume-title":"MICRO-39","author":"Isci C.","year":"2006","unstructured":"C. Isci An analysis of multi-core global power management policies . In MICRO-39 , Dec 2006 . C. Isci et al. An analysis of multi-core global power management policies. In MICRO-39, Dec 2006."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.30"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"e_1_2_1_9_1","volume-title":"2nd Workshop on Design, Architecture and Simulation of CMP Platforms (dasCMP\/Micro)","author":"H.","year":"2006","unstructured":"H. Kannan et. al. From chaos to QoS: Case studies in CMP resource management . In 2nd Workshop on Design, Architecture and Simulation of CMP Platforms (dasCMP\/Micro) , 2006 . H. Kannan et. al. From chaos to QoS: Case studies in CMP resource management. In 2nd Workshop on Design, Architecture and Simulation of CMP Platforms (dasCMP\/Micro), 2006."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542342"},{"key":"e_1_2_1_11_1","volume-title":"HPCA","author":"Lin J.","year":"2008","unstructured":"J. Lin Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems . In HPCA , 2008 . J. Lin et al. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In HPCA, 2008."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283791"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250671"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152160"},{"volume-title":"Intel Technology Journal","year":"2006","key":"e_1_2_1_16_1","unstructured":"Naveh et. al. Power and thermal management in the Intel R\u00aecoreTM duo processor . In Intel Technology Journal , 2006 . Naveh et. al. Power and thermal management in the Intel R\u00aecoreTM duo processor. In Intel Technology Journal, 2006."},{"key":"e_1_2_1_17_1","volume-title":"Intel Technology Journal","author":"R.","year":"2007","unstructured":"R. Iyer et. al. Datacenter-on-chip architectures : Tera-scale challenges and opportunities . In Intel Technology Journal , 2007 . R. Iyer et. al. Datacenter-on-chip architectures : Tera-scale challenges and opportunities. In Intel Technology Journal, 2007."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_2_1_24_1","volume-title":"MICRO","author":"F.","year":"2008","unstructured":"Jose F. Martinez Ramazan Bitirgen, Engin Ipek. Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach . In MICRO , 2008 . Jose F. Martinez Ramazan Bitirgen, Engin Ipek. Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. In MICRO, 2008."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279377"},{"volume-title":"White Paper","author":"Tsao H.","key":"e_1_2_1_26_1","unstructured":"H. Tsao . Ibm @eserver p5 57 0 server consolidation using POWER5. In White Paper , IBM Corporation . H. Tsao. Ibm @eserver p5 570 server consolidation using POWER5. In White Paper, IBM Corporation."}],"container-title":["ACM SIGMETRICS Performance Evaluation Review"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1773394.1773396","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1773394.1773396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:27Z","timestamp":1750246767000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1773394.1773396"}},"subtitle":["QoS and performance management in CMP architectures"],"short-title":[],"issued":{"date-parts":[[2010,3,27]]},"references-count":26,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2010,3,27]]}},"alternative-id":["10.1145\/1773394.1773396"],"URL":"https:\/\/doi.org\/10.1145\/1773394.1773396","relation":{},"ISSN":["0163-5999"],"issn-type":[{"type":"print","value":"0163-5999"}],"subject":[],"published":{"date-parts":[[2010,3,27]]},"assertion":[{"value":"2010-03-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}