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To deploy PCM as a DRAM alternative and to exploit its scalability, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.<\/jats:p>\n          <jats:p>We propose architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6\u00d7 slower and requires 2.2\u00d7 more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2\u00d7 and 1.0\u00d7, using narrow rows to mitigate write energy as well as multiple rows to improve locality and write coalescing. Partial writes mitigate limited memory endurance to provide more than 10 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.<\/jats:p>","DOI":"10.1145\/1785414.1785441","type":"journal-article","created":{"date-parts":[[2010,6,25]],"date-time":"2010-06-25T17:43:38Z","timestamp":1277487818000},"page":"99-106","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":96,"title":["Phase change memory architecture and the quest for scalability"],"prefix":"10.1145","volume":"53","author":[{"given":"Benjamin C.","family":"Lee","sequence":"first","affiliation":[{"name":"Stanford University"}]},{"given":"Engin","family":"Ipek","sequence":"additional","affiliation":[{"name":"University of Rochester"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[{"name":"Microsoft Research"}]}],"member":"320","published-online":{"date-parts":[[2010,7]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"2","volume":"11","author":"Aslot V.","year":"2003","journal-title":"Sci. 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