{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:08Z","timestamp":1750307408979,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,5,16]],"date-time":"2010-05-16T00:00:00Z","timestamp":1273968000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,5,16]]},"DOI":"10.1145\/1785481.1785507","type":"proceedings-article","created":{"date-parts":[[2010,5,18]],"date-time":"2010-05-18T13:46:25Z","timestamp":1274190385000},"page":"107-110","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["An effective approach for large scale floorplanning"],"prefix":"10.1145","author":[{"given":"Ameya R.","family":"Agnihotri","sequence":"first","affiliation":[{"name":"SUNY Binghamton, Binghamton, NY, USA"}]},{"given":"Satoshi","family":"Ono","sequence":"additional","affiliation":[{"name":"SUNY Binghamton, Binghamton, NY, USA"}]},{"given":"Patrick H.","family":"Madden","sequence":"additional","affiliation":[{"name":"SUNY Binghamton, Binghamton, NY, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,5,16]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382639"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846363"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009907"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065733"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343716"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300032"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.892854"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120838"},{"key":"e_1_3_2_1_10_1","volume-title":"US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design","author":"Hill D.","year":"2002","unstructured":"D. Hill . US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design , 2002 . D. Hill. US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design, 2002."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055187"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266273"},{"key":"e_1_3_2_1_13_1","first-page":"536","article-title":"Standard block architecture for integrated circuit design","volume":"6","author":"Katsioulas A.","year":"2003","unstructured":"A. Katsioulas , S. Chow , J. Avidan , and D. Fotakis . Standard block architecture for integrated circuit design . US Patent 6 , 536 ,028 B1, March 2003 . A. Katsioulas, S. Chow, J. Avidan, and D. Fotakis. Standard block architecture for integrated circuit design. US Patent 6,536,028 B1, March 2003.","journal-title":"US Patent"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123024"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123047"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.552084"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055182"},{"key":"e_1_3_2_1_18_1","volume-title":"June 2004-December","author":"SRC.","year":"2005","unstructured":"SRC. SRC needs document: Logical, physical, and electrical design and analysis tools , June 2004-December 2005 . SRC. SRC needs document: Logical, physical, and electrical design and analysis tools, June 2004-December 2005."}],"event":{"name":"GLSVLSI '10: Great Lakes Symposium on VLSI 2010","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Providence Rhode Island USA","acronym":"GLSVLSI '10"},"container-title":["Proceedings of the 20th symposium on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1785481.1785507","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1785481.1785507","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:31Z","timestamp":1750246771000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1785481.1785507"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5,16]]},"references-count":18,"alternative-id":["10.1145\/1785481.1785507","10.1145\/1785481"],"URL":"https:\/\/doi.org\/10.1145\/1785481.1785507","relation":{},"subject":[],"published":{"date-parts":[[2010,5,16]]},"assertion":[{"value":"2010-05-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}