{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:09Z","timestamp":1750307409613,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":9,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,5,16]],"date-time":"2010-05-16T00:00:00Z","timestamp":1273968000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,5,16]]},"DOI":"10.1145\/1785481.1785566","type":"proceedings-article","created":{"date-parts":[[2010,5,18]],"date-time":"2010-05-18T13:46:25Z","timestamp":1274190385000},"page":"369-372","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers"],"prefix":"10.1145","author":[{"given":"Sumanth","family":"Amarchinta","sequence":"first","affiliation":[{"name":"Rochester Institute of Technology, Rochester, NY, USA"}]},{"given":"Dhireesha","family":"Kudithipudi","sequence":"additional","affiliation":[{"name":"Rochester Institute of Technology, Rochester, NY, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,5,16]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"07458","article-title":"Cmos vlsi design: a circuit and systems perspective. Pearson Education, One Lake Street Upper Saddle River","author":"Weste H. E.","year":"2004","journal-title":"NJ"},{"key":"e_1_3_2_1_2_1","first-page":"10013","article-title":"Sub-threshold design for ultra low-power systems. Springer US, 233 Spring Street New York","author":"Calhoun B. H.","year":"2006","journal-title":"NY"},{"key":"e_1_3_2_1_3_1","first-page":"07458","article-title":"Digital integrated circuits: a design perspective. Pearson Education, One Lake Street Upper Saddle River","author":"Rabaey J. M.","year":"2004","journal-title":"NJ"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344187"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016568.1016639"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915455"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1356802.1356881"},{"volume-title":"IEEE workshop on Unique Chips and Systems","year":"2009","author":"Kanitkar H.","key":"e_1_3_2_1_9_1"}],"event":{"name":"GLSVLSI '10: Great Lakes Symposium on VLSI 2010","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Providence Rhode Island USA","acronym":"GLSVLSI '10"},"container-title":["Proceedings of the 20th symposium on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1785481.1785566","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1785481.1785566","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:31Z","timestamp":1750246771000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1785481.1785566"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5,16]]},"references-count":9,"alternative-id":["10.1145\/1785481.1785566","10.1145\/1785481"],"URL":"https:\/\/doi.org\/10.1145\/1785481.1785566","relation":{},"subject":[],"published":{"date-parts":[[2010,5,16]]},"assertion":[{"value":"2010-05-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}