{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:47:37Z","timestamp":1759146457431,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,5,16]],"date-time":"2010-05-16T00:00:00Z","timestamp":1273968000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,5,16]]},"DOI":"10.1145\/1785481.1785570","type":"proceedings-article","created":{"date-parts":[[2010,5,18]],"date-time":"2010-05-18T13:46:25Z","timestamp":1274190385000},"page":"385-388","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Out-of-order issue logic using sorting networks"],"prefix":"10.1145","author":[{"given":"Siddhesh S.","family":"Mhambrey","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lawrence T.","family":"Clark","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satendra Kumar","family":"Maurya","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krzysztof S.","family":"Berezowski","sequence":"additional","affiliation":[{"name":"Grenoble-INP, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,5,16]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Johnson M. 1991. Superscalar microprocessor design. Prentice Hall Inc.  Johnson M. 1991. Superscalar microprocessor design. Prentice Hall Inc."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Farrell J.A. and Fischer T.C. Issue logic for a 600-MHz out-of-order execution microprocessor IEEE JSSC 33 5 (May 1998) 707--712.  Farrell J.A. and Fischer T.C. Issue logic for a 600-MHz out-of-order execution microprocessor IEEE JSSC 33 5 (May 1998) 707--712.","DOI":"10.1109\/4.668985"},{"volume-title":"Proc. MICRO-34 (Dec. 1-5","year":"2001","author":"Brown M.D.","key":"e_1_3_2_1_3_1"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2002.1158026"},{"key":"e_1_3_2_1_5_1","unstructured":"Online:http:\/\/www-03.ibm.com\/technology\/foundry\/.  Online:http:\/\/www-03.ibm.com\/technology\/foundry\/."},{"key":"e_1_3_2_1_6_1","first-page":"11","article-title":"A 1.8-GHz Instruction Window Buffer for an Out-of-Order Microprocessor Core","volume":"36","author":"Leenstra J.","year":"2001","journal-title":"IEEE JSSC"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0005"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Vangal S. etal 5-GHz 32-bit integer execution core in 130-nm dual-Vt CMOS. IEEE JSSC 32 11 (Nov. 2002) 1421--1432.  Vangal S. et al. 5-GHz 32-bit integer execution core in 130-nm dual-Vt CMOS. IEEE JSSC 32 11 (Nov. 2002) 1421--1432.","DOI":"10.1109\/JSSC.2002.803944"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379265"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1468075.1468121"}],"event":{"name":"GLSVLSI '10: Great Lakes Symposium on VLSI 2010","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Providence Rhode Island USA","acronym":"GLSVLSI '10"},"container-title":["Proceedings of the 20th symposium on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1785481.1785570","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1785481.1785570","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:31Z","timestamp":1750246771000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1785481.1785570"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5,16]]},"references-count":11,"alternative-id":["10.1145\/1785481.1785570","10.1145\/1785481"],"URL":"https:\/\/doi.org\/10.1145\/1785481.1785570","relation":{},"subject":[],"published":{"date-parts":[[2010,5,16]]},"assertion":[{"value":"2010-05-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}