{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:35:21Z","timestamp":1772724921438,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,5,17]],"date-time":"2010-05-17T00:00:00Z","timestamp":1274054400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,5,17]]},"DOI":"10.1145\/1787275.1787314","type":"proceedings-article","created":{"date-parts":[[2010,5,18]],"date-time":"2010-05-18T13:46:25Z","timestamp":1274190385000},"page":"121-130","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["NCID"],"prefix":"10.1145","author":[{"given":"Li","family":"Zhao","sequence":"first","affiliation":[{"name":"Intel, Hillsboro, USA"}]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[{"name":"Intel, Hillsboro, USA"}]},{"given":"Srihari","family":"Makineni","sequence":"additional","affiliation":[{"name":"Intel, Hillsboro, OR, USA"}]},{"given":"Don","family":"Newell","sequence":"additional","affiliation":[{"name":"Intel, Hillsboro, USA"}]},{"given":"Liqun","family":"Cheng","sequence":"additional","affiliation":[{"name":"Intel, Hillsboro, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,5,17]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"page 73--80","author":"Baer J. L.","year":"1988","unstructured":"J. L. Baer and W .H. Wang . \" On the inclusion properties for multi-level cache hierarchies,\" Proceedings of the 15th Annual International Symposium on Computer Architecture , page 73--80 , 1988 . J. L. Baer and W .H. Wang. \"On the inclusion properties for multi-level cache hierarchies,\" Proceedings of the 15th Annual International Symposium on Computer Architecture, page 73--80, 1988."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339696"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.23"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.39"},{"key":"e_1_3_2_1_8_1","unstructured":"Intel\u00ae Microarchitecture (Nehalem) http:\/\/www.intel.com\/technology\/architecture-silicon\/next-gen\/  Intel\u00ae Microarchitecture (Nehalem) http:\/\/www.intel.com\/technology\/architecture-silicon\/next-gen\/"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192015"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261393"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859640"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.19"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250708"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74939"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_18_1","unstructured":"Sap America Inc. \"SAP Standard Benchmarks \" http:\/\/www.sap.com\/solutions\/benchmark\/index.epx  Sap America Inc. \"SAP Standard Benchmarks \" http:\/\/www.sap.com\/solutions\/benchmark\/index.epx"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"e_1_3_2_1_20_1","unstructured":"SPECjbb2005 http:\/\/www.spec.org\/jbb2005\/  SPECjbb2005 http:\/\/www.spec.org\/jbb2005\/"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.8"},{"key":"e_1_3_2_1_22_1","unstructured":"The TPC-C Benchmark http:\/\/www.tpc.org\/tpcc\/  The TPC-C Benchmark http:\/\/www.tpc.org\/tpcc\/"},{"key":"e_1_3_2_1_23_1","unstructured":"The TPC-E Benchmark http:\/\/www.tpc.org\/tpce\/  The TPC-E Benchmark http:\/\/www.tpc.org\/tpce\/"},{"key":"e_1_3_2_1_24_1","unstructured":"B. Waldecker \"AMD Quad Core Processor Overview\" http:\/\/www.amd.com\/us-en\/Processors\/TechnicalResources\/0 30_182 00.html  B. Waldecker \"AMD Quad Core Processor Overview\" http:\/\/www.amd.com\/us-en\/Processors\/TechnicalResources\/0 30_182 00.html"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.53"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.66"}],"event":{"name":"CF'10: Computing Frontiers Conference","location":"Bertinoro Italy","acronym":"CF'10","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 7th ACM international conference on Computing frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1787275.1787314","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1787275.1787314","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:56Z","timestamp":1750245776000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1787275.1787314"}},"subtitle":["a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies"],"short-title":[],"issued":{"date-parts":[[2010,5,17]]},"references-count":25,"alternative-id":["10.1145\/1787275.1787314","10.1145\/1787275"],"URL":"https:\/\/doi.org\/10.1145\/1787275.1787314","relation":{},"subject":[],"published":{"date-parts":[[2010,5,17]]},"assertion":[{"value":"2010-05-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}