{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:29:31Z","timestamp":1750307371906,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,5,17]],"date-time":"2010-05-17T00:00:00Z","timestamp":1274054400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,5,17]]},"DOI":"10.1145\/1787275.1787316","type":"proceedings-article","created":{"date-parts":[[2010,5,18]],"date-time":"2010-05-18T13:46:25Z","timestamp":1274190385000},"page":"141-150","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Where replacement algorithms fail"],"prefix":"10.1145","author":[{"given":"Georgios","family":"Keramidas","sequence":"first","affiliation":[{"name":"Industrial Systems Institute, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pavlos","family":"Petoumenos","sequence":"additional","affiliation":[{"name":"University of Patras, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefanos","family":"Kaxiras","sequence":"additional","affiliation":[{"name":"University of Patras, Patrras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,5,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"e_1_3_2_1_2_1","volume-title":"Proc. of the International Symposium on Computer Architecture","author":"Chou Y.","year":"2004","unstructured":"Y. Chou , B. Fahs , and S. Abraham . Microarchitecture optimizations for exploring memory-level parallelism . Proc. of the International Symposium on Computer Architecture , 2004 . Y. Chou, B. Fahs, and S. Abraham. Microarchitecture optimizations for exploring memory-level parallelism. Proc. of the International Symposium on Computer Architecture, 2004."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346201"},{"key":"e_1_3_2_1_4_1","volume-title":"8th International Conference on Architectural Support for Programming Languages and Operating Systems","author":"Glew A.","year":"1998","unstructured":"A. Glew . MLP yes! ILP no! In Wild and Crazy Ideas Session , 8th International Conference on Architectural Support for Programming Languages and Operating Systems , 1998 . A. Glew. MLP yes! ILP no! In Wild and Crazy Ideas Session, 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822804"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.817393"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/846234.849348"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006729"},{"key":"e_1_3_2_1_10_1","volume-title":"Timestamp-Based Selective Cache Allocation. In the Workshop on Memory Performance Issues","author":"Karlsson M.","year":"2001","unstructured":"M. Karlsson and E. Hagersten . Timestamp-Based Selective Cache Allocation. In the Workshop on Memory Performance Issues , 2001 . M. Karlsson and E. Hagersten. Timestamp-Based Selective Cache Allocation. In the Workshop on Memory Performance Issues, 2001."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.41"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339669"},{"key":"e_1_3_2_1_15_1","volume-title":"Proc. of the International Symposium on High-Performance Computer Architecture","author":"Lee J.","year":"2001","unstructured":"J. Lee , Y. Solihin and J. Torellas . Automatically mapping code on an intelligent memory architecture . Proc. of the International Symposium on High-Performance Computer Architecture , 2001 . J. Lee, Y. Solihin and J. Torellas. Automatically mapping code on an intelligent memory architecture. Proc. of the International Symposium on High-Performance Computer Architecture, 2001."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"e_1_3_2_1_18_1","author":"Milutinovic V.","year":"1996","unstructured":"V. Milutinovic , B. Markovic , M. Tomasevic , and M. Tremblay . The Split Temporal\/Spatial Cache: Initial Performance analysis. Journal of Systems Architecture: the EUROMICRO Journal , 1996 . V. Milutinovic, B. Markovic, M. Tomasevic, and M. Tremblay. The Split Temporal\/Spatial Cache: Initial Performance analysis. Journal of Systems Architecture: the EUROMICRO Journal, 1996.","journal-title":"Journal of Systems Architecture: the EUROMICRO Journal"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/1812707.1812719"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11950-7_11"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74309-5_11"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.14"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/290940.290973"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006213"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225177"},{"key":"e_1_3_2_1_28_1","volume-title":"Proc. of the International Symposium on High-Performance Computer Architecture","author":"Wong W. A.","year":"2000","unstructured":"W. A. Wong and J. L. Baer . Modified LRU policies for improving second-level cache behavior . Proc. of the International Symposium on High-Performance Computer Architecture , 2000 . W. A. Wong and J. L. Baer. Modified LRU policies for improving second-level cache behavior. Proc. of the International Symposium on High-Performance Computer Architecture, 2000."}],"event":{"name":"CF'10: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Bertinoro Italy","acronym":"CF'10"},"container-title":["Proceedings of the 7th ACM international conference on Computing frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1787275.1787316","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1787275.1787316","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:56Z","timestamp":1750245776000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1787275.1787316"}},"subtitle":["a thorough analysis"],"short-title":[],"issued":{"date-parts":[[2010,5,17]]},"references-count":27,"alternative-id":["10.1145\/1787275.1787316","10.1145\/1787275"],"URL":"https:\/\/doi.org\/10.1145\/1787275.1787316","relation":{},"subject":[],"published":{"date-parts":[[2010,5,17]]},"assertion":[{"value":"2010-05-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}