{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:29:31Z","timestamp":1750307371368,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,6,13]],"date-time":"2010-06-13T00:00:00Z","timestamp":1276387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,6,13]]},"DOI":"10.1145\/1811100.1811121","type":"proceedings-article","created":{"date-parts":[[2010,6,15]],"date-time":"2010-06-15T13:11:04Z","timestamp":1276607464000},"page":"91-96","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Worst-case performance prediction under supply voltage and temperature variation"],"prefix":"10.1145","author":[{"given":"Chung-Kuan","family":"Cheng","sequence":"first","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Kambiz","family":"Samadi","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]},{"given":"Amirali","family":"Shayan","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/1356802.1356868"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812310"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1214\/aos\/1176347963"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e89-c.11.1559"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2004.06.017"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382687"},{"key":"e_1_3_2_1_8_1","volume-title":"Proc. ISQED","author":"Hu X.","year":"2010","unstructured":"X. Hu , D. Peng , A. Shayan and C.-K. Cheng , \"Worst-Case Noise Prediction With Non-Zero Current Transition Times for Early Power Distribution System Verification\" , Proc. ISQED , 2010 . X. Hu, D. Peng, A. Shayan and C.-K. Cheng, \"Worst-Case Noise Prediction With Non-Zero Current Transition Times for Early Power Distribution System Verification\", Proc. ISQED, 2010."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310053"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/987684.987925"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2007.4449513"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.825834"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.901574"},{"key":"e_1_3_2_1_14_1","first-page":"775","volume-title":"ASPDAC","author":"Okumura T.","year":"2010","unstructured":"T. Okumura , F. Minami , K. Shimazaki , K. Kuwada and M. Hashimoto , \" Gate Delay Estimation in STA Under Dynamic Supply Voltage Noise\" Proc . ASPDAC , 2010 , pp. 775 -- 780 . T. Okumura, F. Minami, K. Shimazaki, K. Kuwada and M. Hashimoto, \"Gate Delay Estimation in STA Under Dynamic Supply Voltage Noise\" Proc. ASPDAC, 2010, pp. 775--780."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.825480"},{"key":"e_1_3_2_1_16_1","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"Weste N. H. E.","year":"2003","unstructured":"N. H. E. Weste and D. M. Harris , CMOS VLSI Design: A Circuits and Systems Perspective , Addison Wesley , 2003 . N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley, 2003."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751912"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2005.11.001"},{"key":"e_1_3_2_1_19_1","first-page":"391","volume-title":"Proc. ASPDAC","author":"Zhang W.","year":"2009","unstructured":"W. Zhang , Y. Zhu , W. Yu , A. Shayan , R. Wang , Z. Zhu and C.-K. Cheng , \"Noise Minimization During Power-Up Stage for a Multi-Domain Power Network \", Proc. ASPDAC , 2009 , pp. 391 -- 396 . W. Zhang, Y. Zhu, W. Yu, A. Shayan, R. Wang, Z. Zhu and C.-K. Cheng, \"Noise Minimization During Power-Up Stage for a Multi-Domain Power Network\", Proc. ASPDAC, 2009, pp. 391--396."},{"key":"e_1_3_2_1_20_1","first-page":"119","volume-title":"Proc. ASPDAC,2010","author":"Zhang W.","unstructured":"W. Zhang , L. Zhang , A. Shayan , W. Yu , X. Hu , Z, Zhu, E. Engin and C.-K. Cheng , \"On-Chip Power Power Network Optimization with Decoupling Capacitors and Controlled-ESRs\" , Proc. ASPDAC,2010 , pp. 119 -- 124 . W. Zhang, L. Zhang, A. Shayan, W. Yu, X. Hu, Z, Zhu, E. Engin and C.-K. Cheng, \"On-Chip Power Power Network Optimization with Decoupling Capacitors and Controlled-ESRs\", Proc. ASPDAC,2010, pp. 119--124."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jss.2006.10.049"},{"volume-title":"Apache Design Solutions","year":"2009","key":"e_1_3_2_1_22_1","unstructured":"\"Power Noise Analysis for Next Generation ICs\" , Apache Design Solutions , 2009 . \"Power Noise Analysis for Next Generation ICs\", Apache Design Solutions, 2009."},{"key":"e_1_3_2_1_23_1","unstructured":"MARS User Guide http:\/\/www.salfordsystems.com\/.  MARS User Guide http:\/\/www.salfordsystems.com\/."},{"key":"e_1_3_2_1_24_1","unstructured":"Synopsys HSPICE http:\/\/www.synopsys.com\/.  Synopsys HSPICE http:\/\/www.synopsys.com\/."}],"event":{"name":"SLIP '10: System Level Interconnect Prediction Workshop","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CS"],"location":"Anaheim California USA","acronym":"SLIP '10"},"container-title":["Proceedings of the 12th ACM\/IEEE international workshop on System level interconnect prediction"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1811100.1811121","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1811100.1811121","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:54Z","timestamp":1750245774000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1811100.1811121"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6,13]]},"references-count":24,"alternative-id":["10.1145\/1811100.1811121","10.1145\/1811100"],"URL":"https:\/\/doi.org\/10.1145\/1811100.1811121","relation":{},"subject":[],"published":{"date-parts":[[2010,6,13]]},"assertion":[{"value":"2010-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}