{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:47:12Z","timestamp":1772164032255,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":45,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,6,19]],"date-time":"2010-06-19T00:00:00Z","timestamp":1276905600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,6,19]]},"DOI":"10.1145\/1815961.1815977","type":"proceedings-article","created":{"date-parts":[[2010,6,22]],"date-time":"2010-06-22T08:21:27Z","timestamp":1277194887000},"page":"117-128","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":41,"title":["Silicon-photonic network architectures for scalable, power-efficient multi-chip systems"],"prefix":"10.1145","author":[{"given":"Pranay","family":"Koka","sequence":"first","affiliation":[{"name":"Sun Labs, Oracle, Austin, TX, USA"}]},{"given":"Michael O.","family":"McCracken","sequence":"additional","affiliation":[{"name":"Sun Labs, Oracle, Austin, TX, USA"}]},{"given":"Herb","family":"Schwetman","sequence":"additional","affiliation":[{"name":"Sun Labs, Oracle, Austin, TX, USA"}]},{"given":"Xuezhe","family":"Zheng","sequence":"additional","affiliation":[{"name":"Sun Labs, Oracle, San Diego, CA, USA"}]},{"given":"Ron","family":"Ho","sequence":"additional","affiliation":[{"name":"Sun Labs, Oracle, Menlo Park, CA, USA"}]},{"given":"Ashok V.","family":"Krishnamoorthy","sequence":"additional","affiliation":[{"name":"Sun Labs, Oracle, San Diego, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,6,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"High performance coolers. http:\/\/www.electrovac.com\/sprache2\/n160352\/i229935.html.  High performance coolers. http:\/\/www.electrovac.com\/sprache2\/n160352\/i229935.html."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.32"},{"key":"e_1_3_2_1_4_1","volume-title":"ISSCC","author":"Bell S.","year":"2008","unstructured":"S. Bell , B. Edwards , : A 64-core SoC with mesh interconnect . In ISSCC , 2008 . S. Bell, B. Edwards, et al. Tile64 - processor: A 64-core SoC with mesh interconnect. In ISSCC, 2008."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278623"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1364\/OL.32.002801"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658639"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/GROUP4.2008.4638207"},{"key":"e_1_3_2_1_10_1","volume-title":"Morgan Kaufman","author":"Dally W.","year":"2004","unstructured":"W. Dally , B. Towles , Principles and Practices of Interconnection Networks . Morgan Kaufman , 2004 . W. Dally, B. Towles, et al. Principles and Practices of Interconnection Networks. Morgan Kaufman, 2004."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798252"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831448"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2003.818246"},{"key":"e_1_3_2_1_14_1","volume-title":"ASSCC","author":"Ho R.","year":"2009","unstructured":"R. Ho , J. Lexau , Circuits for silicon photonics on a \"macrochip \". In ASSCC , Nov. 2009 . R. Ho, J. Lexau, et al. Circuits for silicon photonics on a \"macrochip\". In ASSCC, Nov. 2009."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373469"},{"key":"e_1_3_2_1_17_1","unstructured":"Intel. First tick now tock: Next generation Intel microarchitecture. techreport http:\/\/intel.com\/ 2009.  Intel. First tick now tock: Next generation Intel microarchitecture. techreport http:\/\/intel.com\/ 2009."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897165"},{"key":"e_1_3_2_1_19_1","volume-title":"ISSCC","author":"Kanda K.","year":"2003","unstructured":"K. Kanda , D. Antono , 1.27Gb\/s\/pin 3mW\/pin wireless superconnect (WSC) interface scheme . In ISSCC , 2003 . K. Kanda, D. Antono, et al. 1.27Gb\/s\/pin 3mW\/pin wireless superconnect (WSC) interface scheme. In ISSCC, 2003."},{"key":"e_1_3_2_1_20_1","volume-title":"ISSCC","author":"Kim B.","year":"2009","unstructured":"B. Kim , V. Stojanovic , A 4Gb\/s\/ch 356 fJ\/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS . In ISSCC , 2009 . B. Kim, V. Stojanovic, et al. A 4Gb\/s\/ch 356 fJ\/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS. In ISSCC, 2009."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.35"},{"key":"e_1_3_2_1_22_1","volume-title":"MICRO","author":"N.","year":"2006","unstructured":"N. K1rman, M. K1rman, Leveraging optical technology in future bus-based chip multiprocessors . In MICRO , 2006 . N. K1rman, M. K1rman, et al. Leveraging optical technology in future bus-based chip multiprocessors. In MICRO, 2006."},{"key":"e_1_3_2_1_23_1","volume-title":"Exascale computing study: Technology challenges in achieving exascale systems","author":"Kogge P.","year":"2008","unstructured":"P. Kogge , K. Bergman , Exascale computing study: Technology challenges in achieving exascale systems , 2008 . P. Kogge, K. Bergman, et al. Exascale computing study: Technology challenges in achieving exascale systems, 2008."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JQE.2009.2013104"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2020712"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2008.921100"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-opt:20055006"},{"key":"e_1_3_2_1_29_1","volume-title":"ISSCC","author":"Mensink E.","year":"2007","unstructured":"E. Mensink , D. Schinkel , A 0.28pJ\/b 2Gb\/s\/ch transceiver in 90nm CMOS for 10mm on-chip interconnects . In ISSCC , 2007 . E. Mensink, D. Schinkel, et al. A 0.28pJ\/b 2Gb\/s\/ch transceiver in 90nm CMOS for 10mm on-chip interconnects. In ISSCC, 2007."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1115\/InterPACK2009-89355"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1964.3442"},{"key":"e_1_3_2_1_32_1","volume-title":"ISSCC","author":"Nawathe U.","year":"2007","unstructured":"U. Nawathe , M. Hassan , An 8-core 64-thread 64b power-efficient SPARC SoC . In ISSCC , Feb. 2007 . U. Nawathe, M. Hassan, et al. An 8-core 64-thread 64b power-efficient SPARC SoC. In ISSCC, Feb. 2007."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/CLEO.2008.4551588"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555808"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.20"},{"key":"e_1_3_2_1_36_1","volume-title":"International technology roadmap for semiconductors. webpage","author":"Semiconductor Industries Association","year":"2008","unstructured":"Semiconductor Industries Association . International technology roadmap for semiconductors. webpage , 2008 . http:\/\/www.itrs.net\/Links\/2008ITRS\/Home2008.htm. Semiconductor Industries Association. International technology roadmap for semiconductors. webpage, 2008. http:\/\/www.itrs.net\/Links\/2008ITRS\/Home2008.htm."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2007.25"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/66.97812"},{"key":"e_1_3_2_1_39_1","volume-title":"JSSC","author":"Vangal S.","year":"2008","unstructured":"S. Vangal , J. Howard , An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS . JSSC , 2008 . S. Vangal, J. Howard, et al. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. JSSC, 2008."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/GROUP4.2007.4347702"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_43_1","volume-title":"Silicon photonic WDM point-to-point network for multi-chip processor interconnects","author":"Zheng X.","year":"2008","unstructured":"X. Zheng , P. Koka , Silicon photonic WDM point-to-point network for multi-chip processor interconnects . In IEEE Group IV Photonics , 2008 . X. Zheng, P. Koka, et al. Silicon photonic WDM point-to-point network for multi-chip processor interconnects. In IEEE Group IV Photonics, 2008."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1364\/OE.18.003059"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1364\/OE.18.000204"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1364\/OE.18.005151"}],"event":{"name":"ISCA '10: The 37th Annual International Symposium on Computer Architecture","location":"Saint-Malo France","acronym":"ISCA '10","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS"]},"container-title":["Proceedings of the 37th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1815961.1815977","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1815961.1815977","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:39:43Z","timestamp":1750232383000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1815961.1815977"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6,19]]},"references-count":45,"alternative-id":["10.1145\/1815961.1815977","10.1145\/1815961"],"URL":"https:\/\/doi.org\/10.1145\/1815961.1815977","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1816038.1815977","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2010,6,19]]},"assertion":[{"value":"2010-06-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}