{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:23:40Z","timestamp":1772119420197,"version":"3.50.1"},"reference-count":90,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2010,9]]},"abstract":"<jats:p>Power Gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power Gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.<\/jats:p>","DOI":"10.1145\/1835420.1835421","type":"journal-article","created":{"date-parts":[[2010,10,12]],"date-time":"2010-10-12T15:38:13Z","timestamp":1286897893000},"page":"1-37","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":73,"title":["Power gating"],"prefix":"10.1145","volume":"15","author":[{"given":"Youngsoo","family":"Shin","sequence":"first","affiliation":[{"name":"KAIST, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Seomun","sequence":"additional","affiliation":[{"name":"KAIST, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyu-Myung","family":"Choi","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Yongin, Gyeonggi-Do, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takayasu","family":"Sakurai","sequence":"additional","affiliation":[{"name":"University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,10,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821546"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065594"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"},{"key":"e_1_2_1_4_1","first-page":"253","article-title":"Robust SAT-based search algorithm for leakage power reduction","volume":"2451","author":"Aloul F.","year":"2002","unstructured":"}} Aloul , F. , Hassoun , S. , Sakallah , K. , and Blaauw , D. 2002 . Robust SAT-based search algorithm for leakage power reduction . Lecture Notes in Computer Science vol. 2451 , 253 -- 274 . }}Aloul, F., Hassoun, S., Sakallah, K., and Blaauw, D. 2002. Robust SAT-based search algorithm for leakage power reduction. Lecture Notes in Computer Science vol. 2451, 253--274.","journal-title":"Lecture Notes in Computer Science"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514041"},{"key":"e_1_2_1_6_1","volume-title":"Eds","author":"Anis M.","year":"2003","unstructured":"}} Anis , M. and Elmasry , M. , Eds . 2003 . Multi-Threshold CMOS Digital Circuits: Managing Leakage Power. Kluwer Academic Publishers . }}Anis, M. and Elmasry, M., Eds. 2003. Multi-Threshold CMOS Digital Circuits: Managing Leakage Power. Kluwer Academic Publishers."},{"key":"e_1_2_1_7_1","unstructured":"}}Apache. RedHawk-ALP. http:\/\/www.apache-da.com.  }}Apache. RedHawk-ALP. http:\/\/www.apache-da.com."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065705"},{"key":"e_1_2_1_9_1","unstructured":"}}Cadence. 2005. Encounter User Giude.  }}Cadence. 2005. Encounter User Giude."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/96.704931"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Conference on Computer Aided Design. 779--782","author":"Chen Y.","unstructured":"}} Chen , Y. , Juan , D. , Lee , M. , and Chang , S . 2007. An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon . In Proceedings of the International Conference on Computer Aided Design. 779--782 . }}Chen, Y., Juan, D., Lee, M., and Chang, S. 2007. An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. In Proceedings of the International Conference on Computer Aided Design. 779--782."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146944"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393936"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.832930"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.840987"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.124424"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277229"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the International Conference on VLSI Design. 31--38","author":"Duarte D.","unstructured":"}} Duarte , D. , Tsai , Y.-F. , Vijaykrishnan , N. , and Irwin , M. J . 2002. Evaluating run-time techniques for leakage power reduction . In Proceedings of the International Conference on VLSI Design. 31--38 . }}Duarte, D., Tsai, Y.-F., Vijaykrishnan, N., and Irwin, M. J. 2002. Evaluating run-time techniques for leakage power reduction. In Proceedings of the International Conference on VLSI Design. 31--38."},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the Design Automation Conference. 462--468","author":"Eichelberger E.","unstructured":"}} Eichelberger , E. and Williams , T . 1977. A logic design structure for LSI testability . In Proceedings of the Design Automation Conference. 462--468 . }}Eichelberger, E. and Williams, T. 1977. A logic design structure for LSI testability. In Proceedings of the Design Automation Conference. 462--468."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283798"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857313"},{"key":"e_1_2_1_22_1","unstructured":"}}Gururajarao S. Mair H. Scott D. and Ko U. 2006. Ultra low area overhead retention flip-flop for power-down applications. U.S. Patent Application Publication 20060267654.  }}Gururajarao S. Mair H. Scott D. and Ko U. 2006. Ultra low area overhead retention flip-flop for power-down applications. U.S. Patent Application Publication 20060267654."},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the Custom Integrated Circuits Conference. 475--478","author":"Halter J.","unstructured":"}} Halter , J. and Najm , F . 1997. A gate-level leakage power reduction method for ultra-low-power CMOS circuits . In Proceedings of the Custom Integrated Circuits Conference. 475--478 . }}Halter, J. and Najm, F. 1997. A gate-level leakage power reduction method for ultra-low-power CMOS circuits. In Proceedings of the Custom Integrated Circuits Conference. 475--478."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566425"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873218"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.245593"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228786"},{"key":"e_1_2_1_29_1","volume-title":"Proceedings of the Custom Integrated Circuits Conference. 409--412","author":"Inukai T.","unstructured":"}} Inukai , T. , Takamiya , M. , Nose , K. , Kawaguchi , H. , Hiramoto , T. , and Sakurai , T . 2000. Boosted gate MOS (BGMOS): device\/circuit cooperation scheme to achieve leakage-free giga-scale integration . In Proceedings of the Custom Integrated Circuits Conference. 409--412 . }}Inukai, T., Takamiya, M., Nose, K., Kawaguchi, H., Hiramoto, T., and Sakurai, T. 2000. Boosted gate MOS (BGMOS): device\/circuit cooperation scheme to achieve leakage-free giga-scale integration. In Proceedings of the Custom Integrated Circuits Conference. 409--412."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.34"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309976"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885057"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the European Solid-State Circuits Conference. 317--320","author":"Kao J.","unstructured":"}} Kao , J. and Chandrakasan , A . 2001. MTCMOS sequential circuits . In Proceedings of the European Solid-State Circuits Conference. 317--320 . }}Kao, J. and Chandrakasan, A. 2001. MTCMOS sequential circuits. In Proceedings of the European Solid-State Circuits Conference. 317--320."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277180"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.871328"},{"key":"e_1_2_1_36_1","unstructured":"}}Keating M. Flynn D. Aitken R. Gibbons A. and Shi K. 2007. Low Power Methodology Manual For System-on-Chip Design. Springer.   }}Keating M. Flynn D. Aitken R. Gibbons A. and Shi K. 2007. Low Power Methodology Manual For System-on-Chip Design. Springer."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313937"},{"key":"e_1_2_1_38_1","doi-asserted-by":"crossref","DOI":"10.1109\/TCSII.2007.894414","article-title":"Semicustom design methodology of power gated circuits for low leakage applications","author":"Kim H.","year":"2007","unstructured":"}} Kim , H. and Shin , Y. 2007 . Semicustom design methodology of power gated circuits for low leakage applications . IEEE Trans. Circuits Syst. II , 54, 6, 512--516. }}Kim, H. and Shin, Y. 2007. Semicustom design methodology of power gated circuits for low leakage applications. IEEE Trans. Circuits Syst. II, 54, 6, 512--516.","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383125"},{"key":"e_1_2_1_40_1","volume-title":"Proceedings of the Custom Integrated Circuits Conference. 321--324","author":"Kozhaya J.","unstructured":"}} Kozhaya , J. and Bakir , L . 2004. An electrically robust method for placing power gating switches in voltage islands . In Proceedings of the Custom Integrated Circuits Conference. 321--324 . }}Kozhaya, J. and Bakir, L. 2004. An electrically robust method for placing power gating switches in voltage islands. In Proceedings of the Custom Integrated Circuits Conference. 321--324."},{"key":"e_1_2_1_41_1","volume-title":"Proceedings of the Custom Integrated Circuits Conference. 125--128","author":"Krishnamurthy R. K.","unstructured":"}} Krishnamurthy , R. K. , Alvandpour , A. , De , V. , and Borkar , S . 2002. High-performance and low-power challenges for sub-70nm microprocessor circuits . In Proceedings of the Custom Integrated Circuits Conference. 125--128 . }}Krishnamurthy, R. K., Alvandpour, A., De, V., and Borkar, S. 2002. High-performance and low-power challenges for sub-70nm microprocessor circuits. In Proceedings of the Custom Integrated Circuits Conference. 125--128."},{"key":"e_1_2_1_42_1","volume-title":"Proceedings of the Symposium on VLSI Circuits. 44--45","author":"Kumagai K.","unstructured":"}} Kumagai , K. , Iwaki , H. , Yoshida , H. , Suzuki , H. , Yamada , T. , and Kurosawa , S . 1998. A novel powering-down scheme for low Vt CMOS circuits . In Proceedings of the Symposium on VLSI Circuits. 44--45 . }}Kumagai, K., Iwaki, H., Yoshida, H., Suzuki, H., Yamada, T., and Kurosawa, S. 1998. A novel powering-down scheme for low Vt CMOS circuits. In Proceedings of the Symposium on VLSI Circuits. 44--45."},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774601"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775879"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.886528"},{"key":"e_1_2_1_46_1","unstructured":"}}Magma. 2008. Talus Power Pro.  }}Magma. 2008. Talus Power Pro."},{"key":"e_1_2_1_47_1","volume-title":"Proceedings of the Symposium on VLSI Circuits. 224--225","author":"Mair H.","unstructured":"}} Mair , H. , Wang , A. , Gammie , G. , Scott , D. , Royannez , P. , Gururajarao , S. , Chau , M. , Lagerquist , R. , Ho , L. , Basude , M. , Culp , N. , Sadate , A. , Wilson , D. , Dahan , F. , Song , J. , Carlson , B. , and Ko , U . 2007. A 65-nm mobile multimedia applications processor with an adaptive power management scheme to compensate for variations . In Proceedings of the Symposium on VLSI Circuits. 224--225 . }}Mair, H., Wang, A., Gammie, G., Scott, D., Royannez, P., Gururajarao, S., Chau, M., Lagerquist, R., Ho, L., Basude, M., Culp, N., Sadate, A., Wilson, D., Dahan, F., Song, J., Carlson, B., and Ko, U. 2007. A 65-nm mobile multimedia applications processor with an adaptive power management scheme to compensate for variations. In Proceedings of the Symposium on VLSI Circuits. 224--225."},{"key":"e_1_2_1_48_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 400--401","author":"Min K.-S.","unstructured":"}} Min , K.-S. , Kawaguchi , H. , and Sakurai , T . 2003. Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era . In Proceedings of the IEEE International Solid-State Circuits Conference. 400--401 . }}Min, K.-S., Kawaguchi, H., and Sakurai, T. 2003. Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era. In Proceedings of the IEEE International Solid-State Circuits Conference. 400--401."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"e_1_2_1_50_1","volume-title":"Proceedings of the Asia South Pacific Design Automation Conference. 113--116","author":"Mutoh S.","unstructured":"}} Mutoh , S. , Shigematsu , S. , Gotoh , Y. , and Konaka , S . 1999. Design method of MTCMOS power switch for low-voltage high-speed LSIs . In Proceedings of the Asia South Pacific Design Automation Conference. 113--116 . }}Mutoh, S., Shigematsu, S., Gotoh, Y., and Konaka, S. 1999. Design method of MTCMOS power switch for low-voltage high-speed LSIs. In Proceedings of the Asia South Pacific Design Automation Conference. 113--116."},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313932"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383132"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810054"},{"key":"e_1_2_1_54_1","volume-title":"Eds","author":"Narendra S. G.","year":"2005","unstructured":"}} Narendra , S. G. and Chandrakasan , A. , Eds . 2005 . Leakage in Nanometer CMOS Technologies. Springer . }}Narendra, S. G. and Chandrakasan, A., Eds. 2005. Leakage in Nanometer CMOS Technologies. Springer."},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118435"},{"key":"e_1_2_1_56_1","unstructured":"}}OpenCores. 2009. Opencores. http:\/\/www.opencores.org\/.  }}OpenCores. 2009. Opencores. http:\/\/www.opencores.org\/."},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2003297"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810281"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776032"},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775860"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009963"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"e_1_2_1_63_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 138--139","author":"Royannez P.","unstructured":"}} Royannez , P. , Mair , H. , Dahan , F. , Wagner , M. , Streeter , M. , Bouetel , L. , Blasquez , J. , Clasen , H. , Semino , G. , Dong , J. , Scott , D. , Pitts , B. , Raibaut , C. , and Ko , U . 2005. 90nm low leakage SoC design techniques for wireless applications . In Proceedings of the IEEE International Solid-State Circuits Conference. 138--139 . }}Royannez, P., Mair, H., Dahan, F., Wagner, M., Streeter, M., Bouetel, L., Blasquez, J., Clasen, H., Semino, G., Dong, J., Scott, D., Pitts, B., Raibaut, C., and Ko, U. 2005. 90nm low leakage SoC design techniques for wireless applications. In Proceedings of the IEEE International Solid-State Circuits Conference. 138--139."},{"key":"e_1_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885041"},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283803"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006084"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837395"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2033356"},{"key":"e_1_2_1_70_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 318--319","author":"Seta K.","unstructured":"}} Seta , K. , Hara , H. , Kuroda , T. , Kakumu , M. , and Sakurai , T . 1995. 50&percnt; active-power saving without speed degradation using standby power reduction (SPR) circuit . In Proceedings of the IEEE International Solid-State Circuits Conference. 318--319 . }}Seta, K., Hara, H., Kuroda, T., Kakumu, M., and Sakurai, T. 1995. 50&percnt; active-power saving without speed degradation using standby power reduction (SPR) circuit. In Proceedings of the IEEE International Solid-State Circuits Conference. 318--319."},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146943"},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.585288"},{"key":"e_1_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822775"},{"key":"e_1_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.899228"},{"key":"e_1_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2012532"},{"key":"e_1_2_1_76_1","unstructured":"}}Synopsys. 2007. Astro User Guide.  }}Synopsys. 2007. Astro User Guide."},{"key":"e_1_2_1_77_1","unstructured":"}}Synopsys 2008. NanoSim User Guide.  }}Synopsys 2008. NanoSim User Guide."},{"key":"e_1_2_1_78_1","unstructured":"}}Synopsys. 2010. IC Compiler Design Planning User Guide.  }}Synopsys. 2010. IC Compiler Design Planning User Guide."},{"key":"e_1_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1587\/elex.3.281"},{"key":"e_1_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818291"},{"key":"e_1_2_1_81_1","unstructured":"}}TSMC. Reference Flow 7.0. http:\/\/www.tsmc.com\/.  }}TSMC. Reference Flow 7.0. http:\/\/www.tsmc.com\/."},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566458"},{"key":"e_1_2_1_84_1","volume-title":"Proceedings of the International Midwest Symposium on Circuits and Systems. 493--496","author":"Usami K.","unstructured":"}} Usami , K. and Yoshioka , H . 2004. A scheme to reduce active leakage power by detecting state transitions . In Proceedings of the International Midwest Symposium on Circuits and Systems. 493--496 . }}Usami, K. and Yoshioka, H. 2004. A scheme to reduce active leakage power by detecting state transitions. In Proceedings of the International Midwest Symposium on Circuits and Systems. 493--496."},{"key":"e_1_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922710"},{"key":"e_1_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871536"},{"key":"e_1_2_1_87_1","volume-title":"Proceedings of the Symposium on VLSI Circuits. 40--41","author":"Ye Y.","unstructured":"}} Ye , Y. , Borkar , S. , and De , V . 1998. A new technique for standby leakage reduction in high-performance circuits . In Proceedings of the Symposium on VLSI Circuits. 40--41 . }}Ye, Y., Borkar, S., and De, V. 1998. A new technique for standby leakage reduction in high-performance circuits. In Proceedings of the Symposium on VLSI Circuits. 40--41."},{"key":"e_1_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065596"},{"key":"e_1_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.980256"},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566436"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1835420.1835421","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1835420.1835421","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:08:44Z","timestamp":1750248524000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1835420.1835421"}},"subtitle":["Circuits, design methodologies, and best practice for standard-cell VLSI designs"],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":90,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2010,9]]}},"alternative-id":["10.1145\/1835420.1835421"],"URL":"https:\/\/doi.org\/10.1145\/1835420.1835421","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,9]]},"assertion":[{"value":"2009-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-10-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}