{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:13Z","timestamp":1750307413304,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,6,13]],"date-time":"2010-06-13T00:00:00Z","timestamp":1276387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS 0509440CCF 0811834CNS 0832108"],"award-info":[{"award-number":["CNS 0509440CCF 0811834CNS 0832108"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CNS 0509440CCF 0811834CNS 0832108"],"award-info":[{"award-number":["CNS 0509440CCF 0811834CNS 0832108"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,6,13]]},"DOI":"10.1145\/1837274.1837286","type":"proceedings-article","created":{"date-parts":[[2010,10,28]],"date-time":"2010-10-28T14:47:40Z","timestamp":1288277260000},"page":"36-41","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["LATA"],"prefix":"10.1145","author":[{"given":"Jilong","family":"Kuang","sequence":"first","affiliation":[{"name":"Unviersity of California, Riverside, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laxmi","family":"Bhuyan","sequence":"additional","affiliation":[{"name":"Unviersity of California, Riverside, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Intel IXP2XXX Product Line of Network Processors. http:\/\/int.xscale-freak.com\/XSDoc\/IXP2xxx\/IXP2xxx_index.htm.  Intel IXP2XXX Product Line of Network Processors. http:\/\/int.xscale-freak.com\/XSDoc\/IXP2xxx\/IXP2xxx_index.htm."},{"key":"e_1_3_2_1_2_1","unstructured":"Intel Xeon Machine. http:\/\/www.Intel.com\/Xeon.  Intel Xeon Machine. http:\/\/www.Intel.com\/Xeon."},{"key":"e_1_3_2_1_3_1","unstructured":"Lmbench. http:\/\/www.bitmover.com\/lmbench\/index.html.  Lmbench. http:\/\/www.bitmover.com\/lmbench\/index.html."},{"key":"e_1_3_2_1_4_1","unstructured":"Machine-SUIF Harvard University. http:\/\/eecs.harvard.edu\/hube\/software\/nci\/overview.html.  Machine-SUIF Harvard University. http:\/\/eecs.harvard.edu\/hube\/software\/nci\/overview.html."},{"key":"e_1_3_2_1_5_1","unstructured":"NetFPGA. http:\/\/www.netfpga.org\/.  NetFPGA. http:\/\/www.netfpga.org\/."},{"key":"e_1_3_2_1_6_1","unstructured":"Papi. http:\/\/icl.cs.utk.edu\/papi\/.  Papi. http:\/\/icl.cs.utk.edu\/papi\/."},{"key":"e_1_3_2_1_7_1","unstructured":"SUIF Compiler System. http:\/\/suif.stanford.edu\/.  SUIF Compiler System. http:\/\/suif.stanford.edu\/."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/361604.361619"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/166237.166245"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065038"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065039"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.476197"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/24039.24041"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.242154"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1477942.1477952"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/344588.344618"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.503762"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1323548.1323563"},{"volume-title":"Proc. of ICCAD '01","author":"Memik G.","key":"e_1_3_2_1_19_1","unstructured":"G. Memik , W. Mangione-Smith , and W. Hu . Netbench: A bench-marking suite for network processors . In Proc. of ICCAD '01 . G. Memik, W. Mangione-Smith, and W. Hu. Netbench: A bench-marking suite for network processors. In Proc. of ICCAD '01."},{"key":"e_1_3_2_1_20_1","volume-title":"May","author":"VIDIA.","year":"2006","unstructured":"n VIDIA. Firstpacket technology improved system performance. nVIDIA Technical Brief TB-02434-001_v01 , May 2006 . nVIDIA. Firstpacket technology improved system performance. nVIDIA Technical Brief TB-02434-001_v01, May 2006."},{"volume-title":"Proc. of WWWC-6 '03","author":"Ramaswamy R.","key":"e_1_3_2_1_21_1","unstructured":"R. Ramaswamy and T. Wolf . Packetbench: A tool for workload characterization of network processing . In Proc. of WWWC-6 '03 . R. Ramaswamy and T. Wolf. Packetbench: A tool for workload characterization of network processing. In Proc. of WWWC-6 '03."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","DOI":"10.1002\/0470121173","volume-title":"Task Scheduling For Parallel Systems","author":"Sinnen O.","year":"2007","unstructured":"O. Sinnen . Task Scheduling For Parallel Systems . John Wiley & amp; Sons, Inc., Hoboken, New Jersey, 2007 . O. Sinnen. Task Scheduling For Parallel Systems. John Wiley &amp; Sons, Inc., Hoboken, New Jersey, 2007."},{"volume-title":"Proc. of ANCHOR'04","author":"Weng N.","key":"e_1_3_2_1_23_1","unstructured":"N. Weng and T. Wolf . Pipelining vs multiprocessors-choosing the right network processor system topology . In Proc. of ANCHOR'04 . N. Weng and T. Wolf. Pipelining vs multiprocessors-choosing the right network processor system topology. In Proc. of ANCHOR'04."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.308533"},{"volume-title":"Proc. of Globecom '05","author":"Yao J.","key":"e_1_3_2_1_25_1","unstructured":"J. Yao , Y. Luo , L. Bhuyan , and R. Iyer . Optimal network processor topologies for efficient packet processing . In Proc. of Globecom '05 . J. Yao, Y. Luo, L. Bhuyan, and R. Iyer. Optimal network processor topologies for efficient packet processing. In Proc. of Globecom '05."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278681"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.1989.101456"}],"event":{"name":"DAC '10: The 47th Annual Design Automation Conference 2010","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA"],"location":"Anaheim California","acronym":"DAC '10"},"container-title":["Proceedings of the 47th Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1837274.1837286","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1837274.1837286","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:35Z","timestamp":1750246775000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1837274.1837286"}},"subtitle":["a latency and throughput-aware packet processing system"],"short-title":[],"issued":{"date-parts":[[2010,6,13]]},"references-count":27,"alternative-id":["10.1145\/1837274.1837286","10.1145\/1837274"],"URL":"https:\/\/doi.org\/10.1145\/1837274.1837286","relation":{},"subject":[],"published":{"date-parts":[[2010,6,13]]},"assertion":[{"value":"2010-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}