{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:13Z","timestamp":1750307413838,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,6,13]],"date-time":"2010-06-13T00:00:00Z","timestamp":1276387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,6,13]]},"DOI":"10.1145\/1837274.1837364","type":"proceedings-article","created":{"date-parts":[[2010,10,28]],"date-time":"2010-10-28T14:47:40Z","timestamp":1288277260000},"page":"356-361","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["SCUD"],"prefix":"10.1145","author":[{"given":"Mohammad Shihabul","family":"Haque","sequence":"first","affiliation":[{"name":"University of New South Wales, Sydney, Australia"}]},{"given":"Jorgen","family":"Peddersen","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, Australia"}]},{"given":"Andhi","family":"Janapsatya","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, Australia"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[{"name":"University of New South Wales, Sydney, Australia"}]}],"member":"320","published-online":{"date-parts":[[2010,6,13]]},"reference":[{"unstructured":"Intel xscale microprocessor data book. www.intel.com.  Intel xscale microprocessor data book. www.intel.com.","key":"e_1_3_2_1_1_1"},{"unstructured":"Xtensa processor. http:\/\/www.tensilica.com\/.  Xtensa processor. http:\/\/www.tensilica.com\/.","key":"e_1_3_2_1_2_1"},{"unstructured":"Xtensa lx2 data book. www.tensilica.com. 3\/2007.  Xtensa lx2 data book. www.tensilica.com. 3\/2007.","key":"e_1_3_2_1_3_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1145\/986537.986601"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1145\/339647.339657"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1145\/268806.268810"},{"unstructured":"J. Edler and M. D. Hill. Dinero iv trace-driven uniprocessor cache simulator. http:\/\/www.cs.wisc.edu\/markhill\/DineroIV\/ 2004.  J. Edler and M. D. Hill. Dinero iv trace-driven uniprocessor cache simulator. http:\/\/www.cs.wisc.edu\/markhill\/DineroIV\/ 2004.","key":"e_1_3_2_1_7_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1145\/371636.371752"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1147\/sj.92.0078"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1145\/325478.325479"},{"key":"e_1_3_2_1_11_1","volume-title":"Journal of Instruction Level Parallel","author":"Greg H.","year":"2005","unstructured":"H. Greg , P. Erez , L. Jeremy , and C. Brad . Simpoint 3.0: Faster and more flexible program analysis . In Journal of Instruction Level Parallel , 2005 . H. Greg, P. Erez, L. Jeremy, and C. Brad. Simpoint 3.0: Faster and more flexible program analysis. In Journal of Instruction Level Parallel, 2005."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1145\/1629435.1629476"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.5555\/1870926.1871044"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/12.40842"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1145\/1118299.1118482"},{"key":"e_1_3_2_1_17_1","volume-title":"Flix: Fast relief for performance-hungry embedded applications. Technical report","author":"Leibson S.","year":"2005","unstructured":"S. Leibson and J. Massingham . Flix: Fast relief for performance-hungry embedded applications. Technical report , Tensilica Inc ., 2005 . S. Leibson and J. Massingham. Flix: Fast relief for performance-hungry embedded applications. Technical report, Tensilica Inc., 2005."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1145\/1006209.1006227"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1145\/996566.996652"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.5555\/882452.874337"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1145\/200912.200918"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_22_1","DOI":"10.5555\/1509633.1509815"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_23_1","DOI":"10.1145\/973097.973099"}],"event":{"sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA"],"acronym":"DAC '10","name":"DAC '10: The 47th Annual Design Automation Conference 2010","location":"Anaheim California"},"container-title":["Proceedings of the 47th Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1837274.1837364","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1837274.1837364","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:35Z","timestamp":1750246775000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1837274.1837364"}},"subtitle":["a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy"],"short-title":[],"issued":{"date-parts":[[2010,6,13]]},"references-count":22,"alternative-id":["10.1145\/1837274.1837364","10.1145\/1837274"],"URL":"https:\/\/doi.org\/10.1145\/1837274.1837364","relation":{},"subject":[],"published":{"date-parts":[[2010,6,13]]},"assertion":[{"value":"2010-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}