{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:12Z","timestamp":1750307412996,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,6,13]],"date-time":"2010-06-13T00:00:00Z","timestamp":1276387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,6,13]]},"DOI":"10.1145\/1837274.1837384","type":"proceedings-article","created":{"date-parts":[[2010,10,28]],"date-time":"2010-10-28T14:47:40Z","timestamp":1288277260000},"page":"437-442","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Trace-driven optimization of networks-on-chip configurations"],"prefix":"10.1145","author":[{"given":"Andrew B.","family":"Kahng","sequence":"first","affiliation":[{"name":"University of California San Diego, La Jolla, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bill","family":"Lin","sequence":"additional","affiliation":[{"name":"University of California San Diego, La Jolla, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kambiz","family":"Samadi","sequence":"additional","affiliation":[{"name":"University of California San Diego, La Jolla, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rohit Sunkam","family":"Ramanujam","sequence":"additional","affiliation":[{"name":"University of California San Diego, La Jolla, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403676"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/968879.969158"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01660031"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_6_1","volume-title":"Morgan Kaufmann","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles , Principles and Practices of Interconnection Networks , Morgan Kaufmann , 2004 . W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.77"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882474"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.169"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874721"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1323548.1323561"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.77"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"e_1_3_2_1_14_1","first-page":"95","volume-title":"Proc. DATE","author":"Manolache S.","year":"2006","unstructured":"S. Manolache , P. Eles and Z. Peng , \" Buffer Space Optimization with Communication Synthesis and Traffic Shaping for NoCs \", Proc. DATE , 2006 , pp. 95 -- 98 . S. Manolache, P. Eles and Z. Peng, \"Buffer Space Optimization with Communication Synthesis and Traffic Shaping for NoCs\", Proc. DATE, 2006, pp. 95--98."},{"issue":"4","key":"e_1_3_2_1_15_1","first-page":"371","article-title":"The Chip is Network: Toward a Science of Network-on-Chip Design","volume":"2","author":"Marculescu R.","year":"2007","unstructured":"R. Marculescu and P. Bogdan , \" The Chip is Network: Toward a Science of Network-on-Chip Design \", Foundations and Trends in EDA 2 ( 4 ), 2007 , pp. 371 -- 461 . R. Marculescu and P. Bogdan, \"The Chip is Network: Toward a Science of Network-on-Chip Design\", Foundations and Trends in EDA 2(4), 2007, pp. 371--461.","journal-title":"Foundations and Trends in EDA"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_17_1","first-page":"2","volume-title":"Proc. DATE","author":"De Micheli G.","year":"2002","unstructured":"G. De Micheli and L. Benini , \" Networks On Chip: A New Paradigm for Systems on Chip Design \", Proc. DATE , 2002 , pp. 2 -- 6 . G. De Micheli and L. Benini, \"Networks On Chip: A New Paradigm for Systems on Chip Design\", Proc. DATE, 2002, pp. 2--6."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/846214.846646"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.50"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/1097107.1097122"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493930"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065728"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822800"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52439"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006733"},{"issue":"1","key":"e_1_3_2_1_26_1","first-page":"46","article-title":"Buffer Sizing for Multimedia Flows in Packet-Switching NoCs","volume":"3","author":"Tedesco L. P.","year":"2008","unstructured":"L. P. Tedesco , N. Calzans and F. Moraes , \" Buffer Sizing for Multimedia Flows in Packet-Switching NoCs \", Journal ICS , 3 ( 1 ), 2008 , pp. 46 -- 56 . L. P. Tedesco, N. Calzans and F. Moraes, \"Buffer Sizing for Multimedia Flows in Packet-Switching NoCs\", Journal ICS, 3(1), 2008, pp. 46--56.","journal-title":"Journal ICS"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514116"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.820523"},{"key":"e_1_3_2_1_29_1","unstructured":"ARM Integrated Multiprocessor Core 2006 http:\/\/www.arm.com\/. ARM Integrated Multiprocessor Core 2006 http:\/\/www.arm.com\/."},{"key":"e_1_3_2_1_30_1","unstructured":"Virtutech AB. Simics full system simulator http:\/\/www.virtutech.com\/. Virtutech AB. Simics full system simulator http:\/\/www.virtutech.com\/."}],"event":{"name":"DAC '10: The 47th Annual Design Automation Conference 2010","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA"],"location":"Anaheim California","acronym":"DAC '10"},"container-title":["Proceedings of the 47th Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1837274.1837384","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1837274.1837384","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:35Z","timestamp":1750246775000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1837274.1837384"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6,13]]},"references-count":29,"alternative-id":["10.1145\/1837274.1837384","10.1145\/1837274"],"URL":"https:\/\/doi.org\/10.1145\/1837274.1837384","relation":{},"subject":[],"published":{"date-parts":[[2010,6,13]]},"assertion":[{"value":"2010-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}