{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,4]],"date-time":"2026-10-04T05:41:50Z","timestamp":1791092510770,"version":"4.1.0"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2010,9]]},"abstract":"<jats:p>In High-Level Synthesis (HLS), extracting parallelism in order to create small and fast circuits is the main advantage of HLS over software execution. Modulo Scheduling (MS) is a technique in which a loop is parallelized by overlapping different parts of successive iterations. This ability to extract parallelism makes MS an attractive synthesis technique for loop acceleration. In this work we consider two problems involved in the use of MS which are central when targeting FPGAs. Current MS scheduling techniques sacrifice execution times in order to meet resource and delay constraints. Let \u201cideal\u201d execution times be the ones that could have been obtained by MS had we ignored resource and delay constraints. Here we pose the opposite problem, which is more suitable for HLS, namely, how to reduce resource constraints without sacrificing the ideal execution time. We focus on reducing the number of memory ports used by the MS synthesis, which we believe is a crucial resource for HLS. In addition to reducing the number of memory ports we consider the need to develop MS techniques that are fast enough to allow interactive synthesis times and repeated applications of the MS to explore different possibilities of synthesizing the circuits. Current solutions for MS synthesis that can handle memory constraints are too slow to support interactive synthesis. We formalize the problem of reducing the number of parallel memory references in every row of the kernel by a novel combinatorial setting. The proposed technique is based on inserting dummy operations in the kernel and by doing so, performing modulo-shift operations such that the maximal number of parallel memory references in a row is reduced. Experimental results suggest improved execution times for the synthesized circuit. The synthesis takes only a few seconds even for large-size loops.<\/jats:p>","DOI":"10.1145\/1839480.1839485","type":"journal-article","created":{"date-parts":[[2010,9,28]],"date-time":"2010-09-28T17:41:41Z","timestamp":1285695701000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs"],"prefix":"10.1145","volume":"3","author":[{"given":"Yosi","family":"Ben-Asher","sequence":"first","affiliation":[{"name":"University of Haifa"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Danny","family":"Meisler","sequence":"additional","affiliation":[{"name":"University of Haifa"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nadav","family":"Rotem","sequence":"additional","affiliation":[{"name":"University of Haifa"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2010,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.10"},{"key":"e_1_2_1_2_1","unstructured":"}}Bailey D. 2010. Nas lernel benchmark program. http:\/\/www.netlib.org\/benchmark\/nas. }} Bailey D. 2010. Nas lernel benchmark program. http:\/\/www.netlib.org\/benchmark\/nas."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.3188"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2006.74"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354889"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/237578.237613"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the Conference on Design, Automation, and Test in Europe (DATE\u201903)","author":"Cardoso J. M. P."},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the SRC TechCon\u201905","author":"Chen D."},{"key":"e_1_2_1_9_1","unstructured":"}}Devadas S. Ghosh A. and K. K. 1994. Logic Synthesis. McGraw-Hill. }} Devadas S. Ghosh A. and K. K. 1994. Logic Synthesis . McGraw-Hill."},{"key":"e_1_2_1_10_1","unstructured":"}}Dongarra J. Luszczek P. and Petitet A. 2010. The linpack benchmark: Past present and future. http:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cpe.728\/abstract. }} Dongarra J. Luszczek P. and Petitet A. 2010. The linpack benchmark: Past present and future. http:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cpe.728\/abstract."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/258915.258933"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626494000363"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/157485.164900"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176321"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/224818.224847"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the Conference on Parallel Architectures and Compilation Techniques (PACT\u201996)","author":"Llosa J.","year":"1996"},{"key":"e_1_2_1_18_1","first-page":"3","article-title":"Memory access optimisation for reconfigurable systems","volume":"148","author":"Luk W.","year":"2001","journal-title":"IEE Proc. Comput. Digital Techn."},{"key":"e_1_2_1_19_1","doi-asserted-by":"crossref","unstructured":"}}McMahon F. H. 2010. Fortrn kernel:mflops. Lawrence Livermore National Laboratory. }} McMahon F. H. 2010. Fortrn kernel:mflops. Lawrence Livermore National Laboratory.","DOI":"10.1063\/pt.4.1418"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES\u201999)","author":"Moisset P."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/375977.375978"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-005-1195-3"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/581630.581637"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.386007"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02577737"},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the Reconfigurable Architecture Workshop.","author":"Weinhardt M.","year":"1997"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the International Conference on Parallel Processing.","author":"Wolfe M.","year":"1991"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775986"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1839480.1839485","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1839480.1839485","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:35Z","timestamp":1750245755000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1839480.1839485"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":29,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2010,9]]}},"alternative-id":["10.1145\/1839480.1839485"],"URL":"https:\/\/doi.org\/10.1145\/1839480.1839485","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,9]]},"assertion":[{"value":"2008-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-09-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}