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Syst."],"published-print":{"date-parts":[[2010,9]]},"abstract":"<jats:p>Optimal reconfigurable hardware implementations may require the use of arbitrary floating-point formats that do not necessarily conform to IEEE specified sizes. We present a variable precision floating-point library (VFloat) that supports general floating-point formats including IEEE standard formats. Most previously published floating-point formats for use with reconfigurable hardware are subsets of our format. Custom datapaths with optimal bitwidths for each operation can be built using the variable precision hardware modules in the VFloat library, enabling a higher level of parallelism. The VFloat library includes three types of hardware modules for format control, arithmetic operations, and conversions between fixed-point and floating-point formats. The format conversions allow for hybrid fixed- and floating-point operations in a single design. This gives the designer control over a large number of design possibilities including format as well as number range within the same application. In this article, we give an overview of the components in the VFloat library and demonstrate their use in an implementation of the K-means clustering algorithm applied to multispectral satellite images.<\/jats:p>","DOI":"10.1145\/1839480.1839486","type":"journal-article","created":{"date-parts":[[2010,9,28]],"date-time":"2010-09-28T17:41:41Z","timestamp":1285695701000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":41,"title":["VFloat"],"prefix":"10.1145","volume":"3","author":[{"given":"Xiaojun","family":"Wang","sequence":"first","affiliation":[{"name":"AMD"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miriam","family":"Leeser","sequence":"additional","affiliation":[{"name":"Northeastern University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,9]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"}}Altera. http:\/\/www.altera.com\/.  }}Altera. http:\/\/www.altera.com\/."},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the 12th International Conference on Field-Programmable Logic and Applications","author":"Belanovi\u0107 P."},{"key":"e_1_2_1_3_1","unstructured":"}}Conti A. 2007. A hardware\/software system for adaptive beamforming. http:\/\/www.ece.neu.edu\/groups\/rcl\/theses\/conti-ms2007.pdf.  }} Conti A. 2007. A hardware\/software system for adaptive beamforming. http:\/\/www.ece.neu.edu\/groups\/rcl\/theses\/conti-ms2007.pdf."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2005.24"},{"key":"e_1_2_1_5_1","first-page":"361","article-title":"Accelerating the computation of the physical parameters involved in transcranial magnetic stimulation using FPGA devices","volume":"10","author":"Cret O.","year":"2007","journal-title":"Romanian J. Inf. Sci. Technol."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the 48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).","author":"Culley R."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers.","volume":"2","author":"Detrey J."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503056"},{"key":"e_1_2_1_9_1","unstructured":"}}Digital Core Design. http:\/\/www.digitalcoredesign.com\/.  }}Digital Core Design. http:\/\/www.digitalcoredesign.com\/."},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the 16th International Conference on Field-Programmable Logic and Applications. IEEE, 733--736","author":"Diniz P. C."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046204"},{"key":"e_1_2_1_12_1","unstructured":"}}Duda R. O. Hart P. E. and Stork D. G. 2001. Pattern Classification 2nd Ed. John Wiley &amp; Sons Inc. New York.   }} Duda R. O. Hart P. E. and Stork D. G. 2001. Pattern Classification 2nd Ed. John Wiley &amp; Sons Inc. New York."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.863031"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the IEEE Workshop on Embedded Systems for Real Time Media Processing.","author":"Etiemble D."},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the 16th Symposium on Integrated Circuits and Systems Design. IEEE Computer Society, 99--104","author":"Filho A. G. S."},{"key":"e_1_2_1_16_1","unstructured":"}}FPLibrary. A VHDL library of parametrisable floating-point and LNS operators for FPGA. http:\/\/www.ens-lyon.fr\/LIP\/Arenaire\/Ware\/FPLibrary\/.  }} FPLibrary . A VHDL library of parametrisable floating-point and LNS operators for FPGA. http:\/\/www.ens-lyon.fr\/LIP\/Arenaire\/Ware\/FPLibrary\/."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 14th International Workshop on Field-Programmable Logic and Applications (FPL). 95--104","author":"Gokhale M."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024495400663"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/103162.103163"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.16"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. CSREA Press.","author":"Govindu G."},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 33rd Asilomar Conference on Signals, Systems, and Computers.","volume":"2","author":"Hung P."},{"key":"e_1_2_1_23_1","unstructured":"}}IEEE Standards Board and ANSI. 1985. IEEE Standard for Binary Floating-Point Arithmetic. IEEE Press. IEEE Std 754-1985.  }} IEEE Standards Board and ANSI . 1985. IEEE Standard for Binary Floating-Point Arithmetic. IEEE Press. IEEE Std 754-1985."},{"key":"e_1_2_1_24_1","unstructured":"}}Lavenier D. 2000. FPGA implementation of the K-means clustering algorithm for hyperspectral images. LAUR 00-3079 Los Alamos National Laboratory.  }} Lavenier D. 2000. FPGA implementation of the K-means clustering algorithm for hyperspectral images. LAUR 00-3079 Los Alamos National Laboratory."},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the 36th Asilomar Conference on Signals, Systems, and Computers.","volume":"2","author":"Lee B."},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the IEEE Sensor Array and Multichannel Signal Processing Workshop. IEEE, 520--524","author":"Leeser M."},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines. 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Kadlec J. Softley C. and Coleman N. 2002. Logarithmic number system and floating-point arithmetics on FPGA. Lecture Notes in Computer Science. vol. 2438. Springer 175--188."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.63"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPAN.2005.18"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2005.1557051"},{"key":"e_1_2_1_36_1","unstructured":"}}Nallatech. http:\/\/www.nallatech.com\/.  }} Nallatech. http:\/\/www.nallatech.com\/."},{"key":"e_1_2_1_37_1","unstructured":"}}Northeastern University Reconfigurable Computing Laboratory. Vfloat: The northeastern variable precision floating point library. http:\/\/www.ece.neu.edu\/groups\/rcl\/projects\/floatingpoint\/.  }} Northeastern University Reconfigurable Computing Laboratory . Vfloat: The northeastern variable precision floating point library. http:\/\/www.ece.neu.edu\/groups\/rcl\/projects\/floatingpoint\/."},{"key":"e_1_2_1_38_1","volume-title":"Proceedings of the IEEE International Conference on Field-Programmable Technology. IEEE, 352--358","author":"Paschalakis S."},{"key":"e_1_2_1_39_1","unstructured":"}}Poznanovic J. D. 2004. Reconfigurable logic for low-power space systems. http:\/\/www.cs.colorado.edu\/department\/publications\/theses\/docs\/bs\/jeffrey_poznanovic.pdf.  }} Poznanovic J. D. 2004. Reconfigurable logic for low-power space systems. http:\/\/www.cs.colorado.edu\/department\/publications\/theses\/docs\/bs\/jeffrey_poznanovic.pdf."},{"key":"e_1_2_1_40_1","unstructured":"}}QinetiQ. Quixilica floating point cores. http:\/\/www.tekmicro.com\/.  }}QinetiQ. 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