{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,20]],"date-time":"2025-07-20T04:26:38Z","timestamp":1752985598175,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2010,9]]},"abstract":"<jats:p>In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages of reconfigurability and parallel processing. In this article, a unified hardware-software approach for the design of our QuadroCore is presented. This design flow is enabled via compiler-driven reconfiguration which matches application-specific characteristics to a fixed set of architectural variations. A special reconfiguration mechanism has been developed that alters the architecture within a single clock cycle.<\/jats:p>\n          <jats:p>The QuadroCore has been implemented on Xilinx XC2V6000 for functional validation and on UMC\u2019s 90nm standard cell technology for performance estimation. A diverse set of applications have been mapped onto the reconfigurable multiprocessor to meet orthogonal performance characteristics in terms of time and power. Speedup measurements show a 2--11 times performance increase in comparison to a single processor. Additionally, the reconfiguration scheme has been applied to save power in data-parallel applications. Gate-level simulations have been performed to measure the power-performance trade-offs for two computationally complex applications. The power reports confirm that introducing this scheme of reconfiguration results in power savings in the range of 15--24%.<\/jats:p>","DOI":"10.1145\/1839480.1839487","type":"journal-article","created":{"date-parts":[[2010,9,28]],"date-time":"2010-09-28T17:41:41Z","timestamp":1285695701000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis"],"prefix":"10.1145","volume":"3","author":[{"given":"Madhura","family":"Purnaprajna","sequence":"first","affiliation":[{"name":"Heinz Nixdorf Institute, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mario","family":"Porrmann","sequence":"additional","affiliation":[{"name":"Heinz Nixdorf Institute, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ulrich","family":"Rueckert","sequence":"additional","affiliation":[{"name":"Heinz Nixdorf Institute, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Hussmann","sequence":"additional","affiliation":[{"name":"University Of Paderborn, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Thies","sequence":"additional","affiliation":[{"name":"University Of Paderborn, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Uwe","family":"Kastens","sequence":"additional","affiliation":[{"name":"University Of Paderborn, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,9]]},"reference":[{"volume-title":"Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD\u201902)","author":"Barretta D.","key":"e_1_2_1_1_1","unstructured":"}} Barretta , D. , Fornaciari , W. , Sami , M. , and Pau , D . 2002. SIMD extension to VLIW multicluster processors for embedded applications . In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD\u201902) . IEEE Computer Society, Los Alamitos, CA, 523. }}Barretta, D., Fornaciari, W., Sami, M., and Pau, D. 2002. SIMD extension to VLIW multicluster processors for embedded applications. In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD\u201902). IEEE Computer Society, Los Alamitos, CA, 523."},{"volume-title":"Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks (LCN\u201903)","author":"Bonorden O.","key":"e_1_2_1_2_1","unstructured":"}} Bonorden , O. , Br\u00fcls , N. , Le , D. K. , Kastens , U. , Meyer auf der Heide, F., Niemann, J.-C., Porrmann, M., Rueckert, U., Slowik, A., and Thies, M. 2003. A holistic methodology for network processor design . In Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks (LCN\u201903) . 583--592. }}Bonorden, O., Br\u00fcls, N., Le, D. K., Kastens, U., Meyer auf der Heide, F., Niemann, J.-C., Porrmann, M., Rueckert, U., Slowik, A., and Thies, M. 2003. A holistic methodology for network processor design. In Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks (LCN\u201903). 583--592."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/76263.76309"},{"volume-title":"Proceedings of the 5th Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 5th IEEE\/ACM International Symposium on Code Generation and Optimization (CGO\u201907)","author":"Dreesen R.","key":"e_1_2_1_5_1","unstructured":"}} Dreesen , R. , Hussmann , M. , Thies , M. , and Kastens , U . 2007. Register allocation for processors with dynamically reconfigurable register banks . In Proceedings of the 5th Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 5th IEEE\/ACM International Symposium on Code Generation and Optimization (CGO\u201907) . }}Dreesen, R., Hussmann, M., Thies, M., and Kastens, U. 2007. Register allocation for processors with dynamically reconfigurable register banks. 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In Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 3rd IEEE\/ACM International Symposium on Code Generation and Optimization (CGO\u201905) . }}Hussmann, M., Thies, M., and Kastens, U. 2005. Parallelizing compilation through load-time scheduling for a superscalar processor family. In Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 3rd IEEE\/ACM International Symposium on Code Generation and Optimization (CGO\u201905)."},{"volume-title":"Proceedings of the Workshop on Application Specific Processors (WASP) held in conjunction with the Embedded Systems Week (CODES+ISSS, EMSOFT, and CASES), 3--10","author":"Hussmann M.","key":"e_1_2_1_15_1","unstructured":"}} Hussmann , M. , Thies , M. , Kastens , U. , Purnaprajna , M. , Porrmann , M. , and Rueckert , U . 2007. Compiler-driven reconfiguration of multiprocessors . In Proceedings of the Workshop on Application Specific Processors (WASP) held in conjunction with the Embedded Systems Week (CODES+ISSS, EMSOFT, and CASES), 3--10 . }}Hussmann, M., Thies, M., Kastens, U., Purnaprajna, M., Porrmann, M., and Rueckert, U. 2007. Compiler-driven reconfiguration of multiprocessors. In Proceedings of the Workshop on Application Specific Processors (WASP) held in conjunction with the Embedded Systems Week (CODES+ISSS, EMSOFT, and CASES), 3--10."},{"volume-title":"Digest of Technical Papers on IEEE International Solid-State Circuits Conference (ISSCC\u201908)","author":"Ito M.","key":"e_1_2_1_16_1","unstructured":"}} Ito , M. , Hattori , T. , Yoshida , Y. , Hayase , K. , Hayashi , T. , Nishii , O. , Yasu , Y. , Hasegawa , A. , Takada , M. , Ito , M. , Mizuno , H. , Uchiyama , K. , Odaka , T. , Shirako , J. , Mase , M. , Kimura , K. , and Kasahara , H . 2008. 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Springer, New York."},{"volume-title":"Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP\u201905)","author":"Lambrechts A.","key":"e_1_2_1_20_1","unstructured":"}} Lambrechts , A. , Raghavan , P. , Leroy , A. , Talavera , G. , Aa , T. , Jayapala , M. , Catthoor , F. , Verkest , D. , Deconinck , G. , Corp oraal, H., Robert , F. , and Carrabina , J . 2005. Power breakdown analysis for a heterogeneous NoC platform running a video application . In Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP\u201905) . 179--184. }}Lambrechts, A., Raghavan, P., Leroy, A., Talavera, G., Aa, T., Jayapala, M., Catthoor, F., Verkest, D., Deconinck, G., Corporaal, H., Robert, F., and Carrabina, J. 2005. Power breakdown analysis for a heterogeneous NoC platform running a video application. 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Morgan Kaufmann Publishers, San Francisco, CA."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/11682127_19"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2006.10.007"},{"volume-title":"Proceedings of the Semiconductor Conference (SCD\u201909)","author":"Porrmann M.","key":"e_1_2_1_27_1","unstructured":"}} Porrmann , M. , Hagemeyer , J. , Romoth , J. , and Strugholtz , M . 2009. Rapid prototyping of next-generation multiprocessor SoCs . In Proceedings of the Semiconductor Conference (SCD\u201909) . }}Porrmann, M., Hagemeyer, J., Romoth, J., and Strugholtz, M. 2009. Rapid prototyping of next-generation multiprocessor SoCs. In Proceedings of the Semiconductor Conference (SCD\u201909)."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403727"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.19"},{"key":"e_1_2_1_30_1","unstructured":"}}Silicore. 2002. Wishbone system-on-chip (SoC) interconnection architecture for portable IP cores. Tech. rep. http:\/\/www.opencores.org.  }} Silicore . 2002. Wishbone system-on-chip (SoC) interconnection architecture for portable IP cores. Tech. rep. http:\/\/www.opencores.org."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346182"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1839480.1839487","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1839480.1839487","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:35Z","timestamp":1750245755000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1839480.1839487"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2010,9]]}},"alternative-id":["10.1145\/1839480.1839487"],"URL":"https:\/\/doi.org\/10.1145\/1839480.1839487","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2010,9]]},"assertion":[{"value":"2008-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-09-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}