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Thread delaying reduces energy consumption by running the core containing the critical thread at maximum frequency while scaling down the frequency and voltage of the cores containing noncritical threads. In this article, we provide an insightful breakdown of thread delaying on a simulated multi-core microprocessor. Thread balancing improves overall performance by giving higher priority to the critical thread in the issue queue of an SMT core. We provide a detailed breakdown of performance results for thread-balancing, identifying performance benefits and limitations. For those benchmarks where a performance benefit is not possible, we introduce a novel thread-balancing mechanism on an SMT core that can reduce energy consumption. We have performed a detailed study on an Intel microprocessor simulator running parallel applications. Thread delaying can reduce energy consumption by 4% to 44% with negligible performance loss. Thread balancing can increase performance by 20% or can reduce energy consumption by 23%.<\/jats:p>","DOI":"10.1145\/1839667.1839671","type":"journal-article","created":{"date-parts":[[2010,10,5]],"date-time":"2010-10-05T14:38:15Z","timestamp":1286289495000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors"],"prefix":"10.1145","volume":"7","author":[{"given":"R.","family":"Rakvic","sequence":"first","affiliation":[{"name":"United States Naval Academy, Annapolis, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Q.","family":"Cai","sequence":"additional","affiliation":[{"name":"Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Magklis","sequence":"additional","affiliation":[{"name":"Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Chaparro","sequence":"additional","affiliation":[{"name":"Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,10,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.51"},{"key":"e_1_2_1_2_1","unstructured":"}}OpenMP Architecture Review Board. 2005. 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