{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:31:18Z","timestamp":1750307478247,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":4,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,8,18]],"date-time":"2010-08-18T00:00:00Z","timestamp":1282089600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,8,18]]},"DOI":"10.1145\/1840845.1840878","type":"proceedings-article","created":{"date-parts":[[2010,8,19]],"date-time":"2010-08-19T13:15:15Z","timestamp":1282223715000},"page":"159-164","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology"],"prefix":"10.1145","author":[{"given":"Martin","family":"Saint-Laurent","sequence":"first","affiliation":[{"name":"Qualcomm, Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Animesh","family":"Datta","sequence":"additional","affiliation":[{"name":"Qualcomm, San Diego, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,8,18]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Low Power Methodology Manual","author":"Keating M.","year":"2007","unstructured":"M. Keating , Low Power Methodology Manual , Chapter 2, Springer , 2007 . M. Keating et al., Low Power Methodology Manual, Chapter 2, Springer, 2007."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.503933"},{"key":"e_1_3_2_1_3_1","volume-title":"IEEE International Solid-State Circuits Conference","author":"Jotwani R.","year":"2010","unstructured":"R. Jotwani SOI CMOS\" , IEEE International Solid-State Circuits Conference , 2010 . R. Jotwani et al., \"An x86--64 Core Implemented in 32nm SOI CMOS\", IEEE International Solid-State Circuits Conference, 2010."},{"key":"e_1_3_2_1_4_1","volume-title":"IEEE Conference on Electron Devices and Solid-State Circuits","author":"Hong L. S.","year":"2003","unstructured":"L. S. Hong and A. K. Wong , \" Clock Gater Standard Cell Design \", IEEE Conference on Electron Devices and Solid-State Circuits , 2003 . L. S. Hong and A. K. Wong, \"Clock Gater Standard Cell Design\", IEEE Conference on Electron Devices and Solid-State Circuits, 2003."}],"event":{"name":"ISLPED'10: International Symposium on Low Power Electronics and Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS"],"location":"Austin Texas USA","acronym":"ISLPED'10"},"container-title":["Proceedings of the 16th ACM\/IEEE international symposium on Low power electronics and design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1840845.1840878","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1840845.1840878","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:08:56Z","timestamp":1750248536000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1840845.1840878"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,8,18]]},"references-count":4,"alternative-id":["10.1145\/1840845.1840878","10.1145\/1840845"],"URL":"https:\/\/doi.org\/10.1145\/1840845.1840878","relation":{},"subject":[],"published":{"date-parts":[[2010,8,18]]},"assertion":[{"value":"2010-08-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}