{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T02:30:52Z","timestamp":1773369052170,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,9,6]],"date-time":"2010-09-06T00:00:00Z","timestamp":1283731200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,9,6]]},"DOI":"10.1145\/1854153.1854167","type":"proceedings-article","created":{"date-parts":[[2010,9,7]],"date-time":"2010-09-07T15:48:28Z","timestamp":1283874508000},"page":"49-53","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["SwitchCraft"],"prefix":"10.1145","author":[{"given":"Vinicius","family":"Callegaro","sequence":"first","affiliation":[{"name":"UFRGS, Porto Alegre - RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Felipe de Souza","family":"Marques","sequence":"additional","affiliation":[{"name":"UFRGS, Porto Alegre - RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos Eduardo","family":"Klock","sequence":"additional","affiliation":[{"name":"UFRGS, Porto Alegre - RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"suffix":"Jr.","given":"Leomar Soares","family":"da Rosa","sequence":"additional","affiliation":[{"name":"UFPel, Pelotas - RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[{"name":"UFRGS, Porto Alegre - RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andr\u00e9 I.","family":"Reis","sequence":"additional","affiliation":[{"name":"UFRGS, Porto Alegre - RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,9,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.895248"},{"key":"e_1_3_2_1_2_1","unstructured":"L. S. Da Rosa Junior \"Automatic Generation and Evaluation of Transistor Networks in Different Logic Styles\" Tese (Programa de P\u00f3s-Gradua\u00e7\u00e3o em Microeletr\u00f4nica) -- Instituto de Inform\u00e1tica UFRGS Porto Alegre. 2008. 147 f.  L. S. Da Rosa Junior \"Automatic Generation and Evaluation of Transistor Networks in Different Logic Styles\" Tese (Programa de P\u00f3s-Gradua\u00e7\u00e3o em Microeletr\u00f4nica) -- Instituto de Inform\u00e1tica UFRGS Porto Alegre. 2008. 147 f."},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of SPIE","author":"Xue J","year":"2005","unstructured":"J Xue , D Al-Khalili , C. N Rozon , \"Technology mapping in library-free logic synthesis \", Proceedings of SPIE , 2005 . J Xue, D Al-Khalili, C. N Rozon, \"Technology mapping in library-free logic synthesis\", Proceedings of SPIE, 2005."},{"key":"e_1_3_2_1_4_1","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey J. M","year":"2005","unstructured":"J. M , Rabaey , A. Chandrakasan and B. Nikolic , \" Digital Integrated Circuits: A Design Perspective \", 2 nd ed. Upper Saddle River: Prentice Hall , 2005 . J. M, Rabaey, A. Chandrakasan and B. Nikolic, \"Digital Integrated Circuits: A Design Perspective\", 2nd ed. Upper Saddle River: Prentice Hall, 2005.","edition":"2"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.800518"},{"key":"e_1_3_2_1_6_1","volume-title":"A Circuits and Systems Perspective","author":"Weste N. H. E.","year":"2005","unstructured":"N. H. E. Weste , D. Harris , \" CMOS VLSI Design : A Circuits and Systems Perspective \", 3 rd ed. Boston : Pearson\/Addison Wesley , 2005 . N. H. E. Weste, D. Harris, \"CMOS VLSI Design: A Circuits and Systems Perspective\", 3rd ed. Boston: Pearson\/Addison Wesley, 2005.","edition":"3"},{"key":"e_1_3_2_1_7_1","first-page":"5649","volume-title":"Logic Circuit Synthesis. In: IEEE International Symposium on Circuits and Systems, ISCAS, 2005, Kobe, Japan. Proceedings& {S.l.:s.n.}","author":"Chu Y.","year":"2005","unstructured":"Y. Lai; Y. Jiang; H. Chu , \" BDD Decomposition for Mixed CMOS\/PTL\" , Logic Circuit Synthesis. In: IEEE International Symposium on Circuits and Systems, ISCAS, 2005, Kobe, Japan. Proceedings& {S.l.:s.n.} , 2005 . p. 5649 -- 5652 . Y. Lai; Y. Jiang; H. Chu, \"BDD Decomposition for Mixed CMOS\/PTL\", Logic Circuit Synthesis. In: IEEE International Symposium on Circuits and Systems, ISCAS, 2005, Kobe, Japan. Proceedings& {S.l.:s.n.}, 2005. p. 5649--5652."},{"key":"e_1_3_2_1_8_1","unstructured":"S. S. Rupesh \"Synthesis for Nanometer Technologies\". 2004. Thesis. University of Minnesota Minnesota USA.  S. S. Rupesh \"Synthesis for Nanometer Technologies\". 2004. Thesis. University of Minnesota Minnesota USA."},{"key":"e_1_3_2_1_11_1","volume-title":"A. I. Reis, R. P. Ribas, \"A Kernel-based Approach for Factoring Logic Functions\" Microelectronics Students Forum (2009 Aug.: Natal, BR-RN). SForum 2009 {recurso eletr\u00f4nico}. CD-ROM {S.l.}, Setembro","author":"Callegaro V.","year":"2009","unstructured":"V. Callegaro , L. S. Da Rosa Junior , A. I. Reis, R. P. Ribas, \"A Kernel-based Approach for Factoring Logic Functions\" Microelectronics Students Forum (2009 Aug.: Natal, BR-RN). SForum 2009 {recurso eletr\u00f4nico}. CD-ROM {S.l.}, Setembro 2009 . V. Callegaro, L. S. Da Rosa Junior, A. I. Reis, R. P. Ribas, \"A Kernel-based Approach for Factoring Logic Functions\" Microelectronics Students Forum (2009 Aug.: Natal, BR-RN). SForum 2009 {recurso eletr\u00f4nico}. CD-ROM {S.l.}, Setembro 2009."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1150343.1150381"},{"key":"e_1_3_2_1_13_1","first-page":"199","volume-title":"Proceedings Los Alamitos: IEEE","author":"Poli R. E. B.","year":"2003","unstructured":"R. E. B. Poli , R. P. Ribas , A. I. Reis , \"Unified Theory to Build Cell-Level Transistor Networks from BDDs\" , Symposium On Integrated Circuits And System Design, SBCCI, S\u00e3o Paulo, Brasil . Proceedings Los Alamitos: IEEE , 2003 . p. 199 -- 204 . R. E. B. Poli, R. P. Ribas, A. I. Reis, \"Unified Theory to Build Cell-Level Transistor Networks from BDDs\", Symposium On Integrated Circuits And System Design, SBCCI, S\u00e3o Paulo, Brasil. Proceedings Los Alamitos: IEEE, 2003. p. 199--204."},{"key":"e_1_3_2_1_14_1","volume-title":"VIII Student Forum on Microelectronics, 2008","author":"Callegaro V.","year":"2008","unstructured":"V. Callegaro , L. S. Da Rosa Junior, A. I. Reis, R. P. Ribas, \"A Graph-based Solution for Dual Transistor Network Generation \", VIII Student Forum on Microelectronics, 2008 , Gramado. VIII Student Forum on Microelectronics Porto Alegre : SBC , 2008 . CDROM. V. Callegaro, L. S. Da Rosa Junior, A. I. Reis, R. P. Ribas, \"A Graph-based Solution for Dual Transistor Network Generation\", VIII Student Forum on Microelectronics, 2008, Gramado. VIII Student Forum on Microelectronics Porto Alegre : SBC, 2008. CDROM."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045084"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/AICCSA.2006.205099"}],"event":{"name":"SBCCI '10: 23rd Symposium on Integrated Circuits and Systems Design","location":"S\u00e3o Paulo Brazil","acronym":"SBCCI '10","sponsor":["SIGDA ACM Special Interest Group on Design Automation","SBMicro","IEEE ICAS","IEEE Circuits and Systems Society","SBC"]},"container-title":["Proceedings of the 23rd symposium on Integrated circuits and system design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1854153.1854167","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1854153.1854167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:22:41Z","timestamp":1750245761000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1854153.1854167"}},"subtitle":["a framework for transistor network design"],"short-title":[],"issued":{"date-parts":[[2010,9,6]]},"references-count":15,"alternative-id":["10.1145\/1854153.1854167","10.1145\/1854153"],"URL":"https:\/\/doi.org\/10.1145\/1854153.1854167","relation":{},"subject":[],"published":{"date-parts":[[2010,9,6]]},"assertion":[{"value":"2010-09-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}