{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:30:32Z","timestamp":1750307432548,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,9,11]],"date-time":"2010-09-11T00:00:00Z","timestamp":1284163200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,9,11]]},"DOI":"10.1145\/1854273.1854297","type":"proceedings-article","created":{"date-parts":[[2010,9,14]],"date-time":"2010-09-14T14:53:20Z","timestamp":1284476000000},"page":"157-168","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Scalable hardware support for conditional parallelization"],"prefix":"10.1145","author":[{"given":"Zheng","family":"Li","sequence":"first","affiliation":[{"name":"INRIA Saclay, Orsay, France"}]},{"given":"Olivier","family":"Certner","sequence":"additional","affiliation":[{"name":"ST Microelectronics & INRIA Saclay, Orsay, France"}]},{"given":"Jose","family":"Duato","sequence":"additional","affiliation":[{"name":"Polytechnic University of Valencia, Valencia, Spain"}]},{"given":"Olivier","family":"Temam","sequence":"additional","affiliation":[{"name":"INRIA Saclay, Orsay, France"}]}],"member":"320","published-online":{"date-parts":[[2010,9,11]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/65.580917"},{"key":"e_1_3_2_1_2_1","volume-title":"University of California","author":"Asanovic Krste","year":"2006","unstructured":"}} Krste Asanovic , Ras Bodik , Bryan Christopher Catanzaro , Joseph James Gebis , Parry Husbands , Kurt Keutzer , David A. Patterson , William Lester Plishker , John Shalf , Samuel Webb Williams , and Katherine A. Yelick . The landscape of parallel computing research: A view from berkeley. Technical Report UCB\/EECS-2006-183, EECS Department , University of California , Berkeley , Dec 2006 . }}Krste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams, and Katherine A. Yelick. The landscape of parallel computing research: A view from berkeley. Technical Report UCB\/EECS-2006-183, EECS Department, University of California, Berkeley, Dec 2006."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.12"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.1992.271316"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.36"},{"key":"e_1_3_2_1_7_1","unstructured":"}}Barney Blaise. Posix threads programming. https:\/\/computing.llnl.gov\/tutorials\/pthreads.  }}Barney Blaise. Posix threads programming. https:\/\/computing.llnl.gov\/tutorials\/pthreads."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/209936.209958"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/800223.806778"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403555"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105742"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636091"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658640"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/4472.4478"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006711"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250683"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.121510"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006717"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.13"},{"issue":"4","key":"e_1_3_2_1_21_1","first-page":"298","article-title":"Intel threading building blocks","volume":"23","author":"Pheatt Chuck","year":"2008","unstructured":"}} Chuck Pheatt . Intel threading building blocks . J. Comput. Small Coll. , 23 ( 4 ): 298 -- 298 , 2008 . }}Chuck Pheatt. Intel threading building blocks. J. Comput. Small Coll., 23(4):298--298, 2008.","journal-title":"J. Comput. Small Coll."},{"key":"e_1_3_2_1_23_1","first-page":"117","volume-title":"ISVLSI '02: Proceedings of the IEEE Computer Society Annual Symposium on VLSI","author":"Shashi Kumar","year":"2002","unstructured":"}} Kumar Shashi , Jantsch Axel , Soininen Juha-Pekka , Forsell Martti , Millberg Mikael , A Uberg Johny , TiensyrjAd'Kari, and Hemani Ahmed . A network on chip architecture and design methodology . In ISVLSI '02: Proceedings of the IEEE Computer Society Annual Symposium on VLSI , page 117 , Washington, DC, USA , 2002 . IEEE Computer Society. }}Kumar Shashi, Jantsch Axel, Soininen Juha-Pekka, Forsell Martti, Millberg Mikael, AUberg Johny, TiensyrjAd'Kari, and Hemani Ahmed. A network on chip architecture and design methodology. In ISVLSI '02: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, page 117, Washington, DC, USA, 2002. IEEE Computer Society."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/976146.976151"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/379539.379563"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.07.009"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.243526"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2007.08.008"}],"event":{"name":"PACT '10: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["IFIP WG 10.3 IFIP working group 10.3 on concurrent systems","IEEE CS TCPP IEEE-CS technical committee on parallel processing","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"],"location":"Vienna Austria","acronym":"PACT '10"},"container-title":["Proceedings of the 19th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1854273.1854297","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1854273.1854297","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:56Z","timestamp":1750246796000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1854273.1854297"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9,11]]},"references-count":27,"alternative-id":["10.1145\/1854273.1854297","10.1145\/1854273"],"URL":"https:\/\/doi.org\/10.1145\/1854273.1854297","relation":{},"subject":[],"published":{"date-parts":[[2010,9,11]]},"assertion":[{"value":"2010-09-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}