{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T20:36:23Z","timestamp":1774384583902,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,9,11]],"date-time":"2010-09-11T00:00:00Z","timestamp":1284163200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,9,11]]},"DOI":"10.1145\/1854273.1854332","type":"proceedings-article","created":{"date-parts":[[2010,9,14]],"date-time":"2010-09-14T14:53:20Z","timestamp":1284476000000},"page":"477-488","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":153,"title":["ATAC"],"prefix":"10.1145","author":[{"given":"George","family":"Kurian","sequence":"first","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]},{"given":"Jason E.","family":"Miller","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]},{"given":"James","family":"Psota","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]},{"given":"Jonathan","family":"Eastep","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]},{"given":"Jifeng","family":"Liu","sequence":"additional","affiliation":[{"name":"Massachusetts Instiute of Technology, Cambridge, MA, USA"}]},{"given":"Jurgen","family":"Michel","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]},{"given":"Lionel C.","family":"Kimerling","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]},{"given":"Anant","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Massachusetts Institute of Technology, Cambridge, MA, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,9,11]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"}}The International Technology Roadmap for Semiconductors (ITRS) Technology Working Groups 2008.  }}The International Technology Roadmap for Semiconductors (ITRS) Technology Working Groups 2008."},{"key":"e_1_3_2_1_2_1","volume-title":"ISCA","author":"Agarwal A.","year":"1988","unstructured":"}} A. Agarwal An evaluation of directory schemes for cache coherence . In ISCA , 1988 . }}A. Agarwal et al. An evaluation of directory schemes for cache coherence. In ISCA, 1988."},{"key":"e_1_3_2_1_3_1","volume-title":"ICPP","author":"Gupta A.","year":"1990","unstructured":"}} A. Gupta Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes . In ICPP , 1990 . }}A. Gupta et al. Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. In ICPP, 1990."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2007.25"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.11"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1364\/OE.15.003916"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.55500"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106995"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.89"},{"key":"e_1_3_2_1_12_1","unstructured":"}}Intel Corporation. Intel's Teraflops Research Chip. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1449.htm.  }}Intel Corporation. Intel's Teraflops Research Chip. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1449.htm."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.17"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1038\/nphoton.2008.99"},{"key":"e_1_3_2_1_15_1","volume-title":"Proc. of the International Society for Optical Engineering (SPIE) 6477","author":"Michel J.","year":"2007","unstructured":"}} J. Michel Advances in Fully CMOS Integrated Photonic Circuits . In Proc. of the International Society for Optical Engineering (SPIE) 6477 , p64770P-1-11, 2007 . }}J. Michel et al. Advances in Fully CMOS Integrated Photonic Circuits. In Proc. of the International Society for Optical Engineering (SPIE) 6477, p64770P-1-11, 2007."},{"key":"e_1_3_2_1_16_1","unstructured":"}}J. Psota etal ATAC: All-to-All Computing Using On-Chip Optical Interconnects. In BARC 1\/2007.  }}J. Psota et al. ATAC: All-to-All Computing Using On-Chip Optical Interconnects. In BARC 1\/2007."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537892"},{"key":"e_1_3_2_1_18_1","volume-title":"Graphite: A Distributed Parallel Simulator for Multicores","year":"2009","unstructured":"}}J.Miller Graphite: A Distributed Parallel Simulator for Multicores . 2009 . }}J.Miller et al. Graphite: A Distributed Parallel Simulator for Multicores. 2009."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1038\/nphoton.2007.84"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.49"},{"key":"e_1_3_2_1_21_1","first-page":"575","volume":"16","author":"Liu J. F.","year":"2008","unstructured":"}} J. F. Liu and J. Michel . High Performance Ge Devices for Electronic-Photonic Integrated Circuits. In ECS Transactions , Vol 16 , p 575 -- 582 , 2008 . }}J. F. Liu and J. Michel. High Performance Ge Devices for Electronic-Photonic Integrated Circuits. In ECS Transactions, Vol 16, p 575--582, 2008.","journal-title":"High Performance Ge Devices for Electronic-Photonic Integrated Circuits. In ECS Transactions"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1117\/12.774576"},{"key":"e_1_3_2_1_23_1","volume-title":"ISCA","author":"Taylor M.","year":"2004","unstructured":"}} M. Taylor Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams . In ISCA , 2004 . }}M. Taylor et al. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In ISCA, 2004."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.53"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.28"},{"key":"e_1_3_2_1_26_1","volume-title":"ISCA","author":"Sweazey P.","year":"1986","unstructured":"}} P. Sweazey A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus . In ISCA , 1986 . }}P. Sweazey et al. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In ISCA, 1986."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555808"},{"key":"e_1_3_2_1_28_1","volume-title":"Optical Interconnects in Next-Generation High-Performance Computers. OIDA 2008 Integration Forum","author":"Schow C.","year":"2008","unstructured":"}} C. Schow . Optical Interconnects in Next-Generation High-Performance Computers. OIDA 2008 Integration Forum , 2008 . }}C. Schow. Optical Interconnects in Next-Generation High-Performance Computers. OIDA 2008 Integration Forum, 2008."},{"key":"e_1_3_2_1_29_1","volume-title":"The SPLASH-2 Programs: Characterization and Methodological Considerations","year":"1995","unstructured":"}}S.Woo The SPLASH-2 Programs: Characterization and Methodological Considerations . 1995 . }}S.Woo et al. The SPLASH-2 Programs: Characterization and Methodological Considerations. 1995."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/379189.379198"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2008.922338"}],"event":{"name":"PACT '10: International Conference on Parallel Architectures and Compilation Techniques","location":"Vienna Austria","acronym":"PACT '10","sponsor":["IFIP WG 10.3 IFIP working group 10.3 on concurrent systems","IEEE CS TCPP IEEE-CS technical committee on parallel processing","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"]},"container-title":["Proceedings of the 19th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1854273.1854332","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1854273.1854332","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:39:56Z","timestamp":1750246796000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1854273.1854332"}},"subtitle":["a 1000-core cache-coherent processor with on-chip optical network"],"short-title":[],"issued":{"date-parts":[[2010,9,11]]},"references-count":31,"alternative-id":["10.1145\/1854273.1854332","10.1145\/1854273"],"URL":"https:\/\/doi.org\/10.1145\/1854273.1854332","relation":{},"subject":[],"published":{"date-parts":[[2010,9,11]]},"assertion":[{"value":"2010-09-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}