{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:28:18Z","timestamp":1750307298928,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2010,12]]},"abstract":"<jats:p>The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially Reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools.<\/jats:p>\n          <jats:p>This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic front-end allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by \u201crecipe\u201d scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system.<\/jats:p>\n          <jats:p>The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs.<\/jats:p>","DOI":"10.1145\/1857927.1857931","type":"journal-article","created":{"date-parts":[[2010,12,20]],"date-time":"2010-12-20T15:55:04Z","timestamp":1292860504000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems"],"prefix":"10.1145","volume":"4","author":[{"given":"K.","family":"K\u0119pa","sequence":"first","affiliation":[{"name":"National University of Ireland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Morgan","sequence":"additional","affiliation":[{"name":"National University of Ireland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Ko\u015bciuszkiewicz","sequence":"additional","affiliation":[{"name":"National University of Ireland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Braun","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Karlsruhe Institute of Technology (KIT)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"H\u00fcbner","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Karlsruhe Institute of Technology (KIT)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Becker","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Karlsruhe Institute of Technology (KIT)"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00641-8_24"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.888404"},{"volume-title":"Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications","author":"Bobda C.","key":"e_1_2_1_3_1","unstructured":"Bobda , C. 2007. Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications . Springer . Bobda, C. 2007. Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications. Springer."},{"volume-title":"Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS\u201906)","author":"Bondhugula U.","key":"e_1_2_1_4_1","unstructured":"Bondhugula , U. , Devulapalli , A. , Fernando , J. , Wyckoff , P. , and Sadayappan , P . 2006. Parallel FPGA-based all-pairs shortest-paths in a directed graph . In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS\u201906) . Bondhugula, U., Devulapalli, A., Fernando, J., Wyckoff, P., and Sadayappan, P. 2006. Parallel FPGA-based all-pairs shortest-paths in a directed graph. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS\u201906)."},{"volume-title":"Proceedings of the Workshop on Reconfigurable Computing Education at the IEEE Computer Society Annual Symposium on VLSI (ISLVSI\u201907)","author":"Claus C.","key":"e_1_2_1_5_1","unstructured":"Claus , C. , Zhang , B. , Hubner , M. , Schmutzler , C. , Becker , J. , and Stechele , W . 2007. An XDL-based busmacro generator for customizable communication interfaces for dynamically and partially reconfigurable systems . In Proceedings of the Workshop on Reconfigurable Computing Education at the IEEE Computer Society Annual Symposium on VLSI (ISLVSI\u201907) . Claus, C., Zhang, B., Hubner, M., Schmutzler, C., Becker, J., and Stechele, W. 2007. An XDL-based busmacro generator for customizable communication interfaces for dynamically and partially reconfigurable systems. In Proceedings of the Workshop on Reconfigurable Computing Education at the IEEE Computer Society Annual Symposium on VLSI (ISLVSI\u201907)."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00641-8_8"},{"volume-title":"Proceedings of 4th Annual FPGA World Conference.","author":"Ehliar A.","key":"e_1_2_1_7_1","unstructured":"Ehliar , A. and Liu , D . 2007. Thinking outside the flow: Creating customized backend tools for Xilinx-based designs . In Proceedings of 4th Annual FPGA World Conference. Ehliar, A. and Liu, D. 2007. Thinking outside the flow: Creating customized backend tools for Xilinx-based designs. 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In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA\u201908)."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.61"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1504\/IJCCBS.2010.031707"},{"volume-title":"Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats (LEET\u201908)","author":"King S. T.","key":"e_1_2_1_16_1","unstructured":"King , S. T. , Tucek , J. , Cozzie , A. , Grier , C. , Jiang , W. , and Zhou , Y . 2008. Designing and implementing malicious hardware . In Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats (LEET\u201908) . USENIX Association. King, S. T., Tucek, J., Cozzie, A., Grier, C., Jiang, W., and Zhou, Y. 2008. Designing and implementing malicious hardware. In Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats (LEET\u201908). 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