{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T08:12:10Z","timestamp":1759133530028,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,10,20]],"date-time":"2010-10-20T00:00:00Z","timestamp":1287532800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0953246"],"award-info":[{"award-number":["CCF-0953246"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,20]]},"DOI":"10.1145\/1868447.1868459","type":"proceedings-article","created":{"date-parts":[[2010,10,26]],"date-time":"2010-10-26T12:36:11Z","timestamp":1288096571000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":47,"title":["Next generation on-chip networks"],"prefix":"10.1145","author":[{"given":"George","family":"Nychis","sequence":"first","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Fallin","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Moscibroda","sequence":"additional","affiliation":[{"name":"Microsoft Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,10,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1015467.1015499"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1964.1088883"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"volume-title":"Morgan Kaufmann","year":"2004","author":"Dally W.","key":"e_1_3_2_1_6_1"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669150"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380859"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798251"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669144"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.77"},{"key":"e_1_3_2_1_13_1","unstructured":"Intel Corporation. Single-chip cloud computer. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm.  Intel Corporation. Single-chip cloud computer. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/964725.633035"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.19"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.10"},{"volume-title":"SIGCOMM","year":"2010","author":"Mohammad A.","key":"e_1_3_2_1_17_1"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.91"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"volume-title":"Performance Evaluation Corporation. SPEC CPU2006","year":"2006","key":"e_1_3_2_1_21_1"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_3_2_1_23_1","unstructured":"Tilera Corporation. Tilera announces the world's first 100-core processor with the new tile-gx family. http:\/\/www.tilera.com\/news_&_events\/press_release_091026.php.  Tilera Corporation. Tilera announces the world's first 100-core processor with the new tile-gx family. http:\/\/www.tilera.com\/news_&_events\/press_release_091026.php."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.89"}],"event":{"name":"Hotnets-X: 10th ACM Workshop on Hot Topics in Networks","sponsor":["SIGCOMM ACM Special Interest Group on Data Communication"],"location":"Monterey California","acronym":"Hotnets-X"},"container-title":["Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1868447.1868459","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1868447.1868459","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:08:54Z","timestamp":1750248534000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1868447.1868459"}},"subtitle":["what kind of congestion control do we need?"],"short-title":[],"issued":{"date-parts":[[2010,10,20]]},"references-count":24,"alternative-id":["10.1145\/1868447.1868459","10.1145\/1868447"],"URL":"https:\/\/doi.org\/10.1145\/1868447.1868459","relation":{},"subject":[],"published":{"date-parts":[[2010,10,20]]},"assertion":[{"value":"2010-10-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}